Table of Contents
Advertisement
R
program the MIIMWRDATA register. Writing to the address of the MIIMCNTL register
starts the MDIO read or write transaction using the physical and register address in the
DCR dataRegLSW register.
The host interface interrupt request registers (IRENABLE and IRSTATUS) and the contents
of the registers are shown in
shown in
Table 3-26: Interrupt Status Register IRSTATUS
Address
Code
0
1
2
3
4
0x3A0
Bit
[0:16]
Reserved.
[17]
Configuration Write Interrupt Request bit.
[18]
Configuration Read Interrupt Request bit.
[19]
Address Filter Write Interrupt Request bit.
[20]
Address Filter Read Interrupt Request bit.
[21]
MDIO Write Interrupt Request bit.
[22]
MDIO Read Interrupt Request bit.
[23]
Statistics IP Read Interrupt Request bit.
[24]
Reserved.
[25]
Configuration Write Interrupt Request bit.
[26]
Configuration Read Interrupt Request bit.
[27]
Address Filter Write Interrupt Request bit.
[28]
Address Filter Read Interrupt Request bit.
[29]
MDIO Write Interrupt Request bit.
[30]
MDIO Read Interrupt Request bit.
[31]
Statistics IP Read Interrupt Request bit.
Notes:
1. For more information on Statistics IP, see
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Table
3-28.
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RESERVED
Description
(1)
(1)
"Interfacing to an FPGA Fabric-Based Statistics Block" in Chapter
www.xilinx.com
Table 3-26
and
Table
3-27. The MIIMWRDATA register is
Host Interface
Ethernet MAC
Default Value
–
0
EMAC1
0
EMAC1
0
EMAC1
0
EMAC1
0
EMAC1
0
EMAC1
0
EMAC1
0
–
0
EMAC0
0
EMAC0
0
EMAC0
0
EMAC0
0
EMAC0
0
EMAC0
0
EMAC0
0
6.
87
Advertisement
Table of Contents
