Xilinx Virtex-4 User Manual page 108

Chapter 4: Physical Interface
hold times of the input GMII receiver signals which are sampled at the GMII IOB input
flip-flops.
Figure 4-8
to the single Ethernet MAC clocking scheme, however, one of the
EMAC#CLIENTTXGMIIMIICLKOUT signals is used for all (both Ethernet MACs)
transmitter logic.
GTX_CLK
TX CLIENT
LOGIC
RX CLIENT
LOGIC
TX CLIENT
LOGIC
RX CLIENT
LOGIC
Figure 4-8: 1 Gb/s GMII Clock Management with Two Ethernet MACs Enabled
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108
shows the GMII clocking scheme with two Ethernet MACs enabled. It is similar
EMAC0
PHYEMAC0GTXCLK
CLIENTEMAC0TXGMIIMIICLKIN
EMAC0CLIENTTXGMIIMIICLKOUT
CLIENTEMAC0TXCLIENTCLKIN
NC
EMAC0CLIENTTXCLIENTCLKOUT
PHYEMAC0TXD[7:0]
PHYEMAC0MIITXCLK
CLIENTEMAC0RXCLIENTCLKIN
NC
EMAC0CLIENTRXCLIENTCLKOUT
PHYEMAC0RXD[7:0]
CLIENTEMAC0DCMLOCKED
PHYEMAC0RXCLK
EMAC1
PHYEMAC1GTXCLK
CLIENTEMAC1TXGMIIMIICLKIN
EMAC1CLIENTTXGMIIMIICLKOUT
CLIENTEMAC1TXCLIENTCLKIN
NC
EMAC1CLIENTTXCLIENTCLKOUT
PHYEMAC1TXD[7:0]
PHYEMAC0MIITXCLK
CLIENTEMAC1RXCLIENTCLKIN
NC
EMAC1CLIENTRXCLIENTCLKOUT
PHYEMAC1RXD[7:0]
CLIENTEMAC1DCMLOCKED
PHYEMAC1RXCLK
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ODDR
OBUF
0 D1
Q
D2
BUFG 1
OBUF
D Q
GND
BUFG DCM
Q D
CLK0
CLKIN
CLKFB
ODDR
OBUF
0 D1
NC
Q
D2
1
OBUF
D Q
GND
DCM
BUFG
Q D
CLK0
CLKIN
CLKFB
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
R
GMII_TX_CLK_0
GMII_TXD_0[7:0]
IBUF
GMII_RXD_#[7:0]
IBUFG
GMII_RX_CLK_#
GMII_TX_CLK_1
GMII_TXD_1[7:0]
IBUF
GMII_RXD_#[7:0]
IBUFG
GMII_RX_CLK_#
UG074_3_54_040609