Xilinx Virtex-4 User Manual page 63

Fpga embedded tri-mode ethernet mac
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Transmitting a PAUSE Control Frame
The client initiates a flow control frame by asserting CLIENTEMAC#PAUSEREQ, when
the pause value is on the CLIENTEMAC#PAUSEVAL[15:0] bus. These signals are
synchronous to CLIENTEMAC#TXCLIENTCLKIN. The timing is shown in
When the Ethernet MAC is configured to support transmit flow control, a PAUSE control
frame is transmitted on the link. When CLIENTEMAC#PAUSEREQ is asserted, the PAUSE
parameter is set to the CLIENTEMAC#PAUSEVAL[15:0] value. This does not disrupt any
frame transmission in progress, but it takes priority over any pending frame transmission.
The PAUSE control frame is transmitted even if the transmitter is in a paused state. An
example of a PAUSE frame (not drawn to scale) is shown in
The pause destination address can be configured using the
pause_time in the PAUSE frame is the value from the CLIENTEMAC#PAUSEVAL[15:0].
Receiving a PAUSE Control Frame
When an error-free frame is received by the Ethernet MAC, it examines the following
information:
If any match is false or the Ethernet MAC flow control logic for the receiver is disabled, the
frame is ignored by the flow control logic and passed up to the client.
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Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
CLIENTEMAC#TXCLIENTCLKIN
CLIENTEMAC#PAUSEREQ
CLIENTEMAC#PAUSEVAL[15:0]
Figure 3-29: Pause Request Timing
Pause Destination
Source
Address
Address
01-80-C2-00-00-01
Figure 3-30: Pause Frame Example
The destination address field is matched against the Ethernet MAC control multicast
address and the configured source address for the Ethernet MAC (see
Registers," page
74).
The LT field is matched against the Ethernet MAC control type code.
If the second match is true, the OPCODE field contents are matched against the
Ethernet MAC control OPCODE.
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64-Byte Data Field
MAC
MAC
Control
Control
Pause
Type
OPCODE
Time
0x8808
0x0001
46-Byte Data Field
"Configuration
Client Interface
Figure
3-29.
ug074_3_31_080805
Figure
3-30.
FCS
ug074_3_32_080805
Registers". The
"Configuration
63

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