Xilinx Virtex-4 User Manual page 159

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Writing to the Multicast Address Table Register of the Address Filter Block
For writing to the desired multicast address table register of the AF block, two write
operations must be performed.
1.
2.
3.
4.
5.
6.
Assuming the DCR base address is 0x0, to write the multicast address 0xFACEDEAFCAFE
to the multicast address table register 0x1 of EMAC1:
Reading the PHY Registers Using MDIO
1.
2.
3.
4.
5.
6.
7.
Assume the DCR base address is 0x0 to read from the PHY address 1 and PHY register
0x0 of EMAC0. MDIO must be enabled by writing to the management configuration
register with the clock divider for MDC. Assuming the host frequency is 50 MHz and the
divider is 0xA, results in an MDC frequency of 2.27 MHz.
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Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Write to dataRegLSW register the multicast address[31:0] to be stored on the desired
multicast address table register.
Write to cntlReg register with the address for multicast address word 0 - 0x388 for
EMAC0 and 0x788 for EMAC1. Set the Write enable bit.
Poll the RDYstatus register until the address configuration write bit is asserted.
Write to dataRegLSW register the multicast address[47:32] with the write mask bit and
the value of the multicast address table register to be accessed.
Write to cntlReg register with the address for multicast address word 1 - 0x38C for
EMAC0 and 0x78C for EMAC1. Set the Write enable bit.
Poll the RDYstatus register until the address configuration write bit is asserted.
// Write the multicast address[31:0] to the dataRegLSW register
mtdcr(0x0 + 13, 0xDEAFCAFE);
// Write the address of EMAC1 Multicast Address Word 0 register to the
// cntlReg register
mtdcr(0x0 + 14, 0x8788);
// Poll the RDYstatus register
while ( !(mfdcr(0x0 + 15) & 0x00001000) );
// MULTI_ADDR Register 1 of AF Block
// Write the multicast address [47:32] with the MULTI_ADDR write mask
// bit to the dataRegLSW register
mtdcr(0x0 + 13, 0x0081FACE);
// Write the address of EMAC1 Multicast Address Word 1 register to the
// cntlReg register
mtdcr(0x0 + 14, 0x878C);
// Poll the RDYstatus register
while ( !(mfdcr(0x0 + 3) & 0x00001000) );
Write to dataRegLSW register with the MDIO enable bit and the clock divider
frequency for MDC.
Write to cntlReg register to write to the Ethernet MAC management configuration
register.
Poll the RDYstatus register until the configuration Write-Ready bit is asserted.
Write to the dataRegLSW register with the PHY address and register to be accessed.
Write to the cntlReg register the decode address for a MDIO address output with the
Read-Enable mask asserted.
Poll the RDYstatus register until the MDIO Read-Ready bit is asserted.
Read from the dataRegLSW, to shows the value of the PHY register being accessed.
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Interfacing to the Processor DCR
159