Xilinx Virtex-4 User Manual page 160

Chapter 6: Use Models
Writing to the PHY Registers Using MDIO
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Assume the DCR base address is 0x0, to write 0x1140 to PHY address 1 and PHY register
0x0 of EMAC1. The isolate bit of the PCS/PMA sublayer is not set, and auto-negotiation is
enabled (see
enabled by writing to the management configuration register with the clock divider for
MDC. Assuming the host frequency is 50 MHz and the divider is 0xA, the result is an MDC
frequency of 2.27 MHz.
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160
// EMAC Management Register 0x340 (EMAC0 Management Configuration)
// Write the data to the EMAC0 Management Configuration register to
// enable MDIO with the clock divider 0xA
mtdcr(0x0 + 13, 0x0000004A);
// Write the address of EMAC0 Management Configuration register to the
// cntlReg register
mtdcr(0x0 + 14, 0x8340);
// Poll the RDYstatus register for writing completion
while ( !(mfdcr(0x0 + 15) & 0x00000040) );
// Write the PHY address and PHY register to be accessed to the
// dataRegLSW register
mtdcr(0x0 + 13, 0x00000020);
// Write the decode address for MDIO address output to the cntlReg
// register
mtdcr(0x0 + 14, 0x03B4);
// Poll the RDYstatus register
while ( !(mfdcr(0x0 + 15) & 0x00000002) );
// Read the dataRegLSW with the values returned from the
// PHY Register 0x0
mfdcr (0x0 + 13);
Write to the dataRegLSW register with the MDIO enable bit and the clock divider
frequency for MDC.
Write to the cntlReg register to write to the Ethernet MAC management configuration
register.
Poll the RDYstatus register until the configuration Write-Ready bit is asserted.
Write to the dataRegLSW register with the data to be written to the PHY register.
Write to the cntlReg register the decode address for MDIO write data.
Write to the dataRegLSW register with the PHY address and register to be accessed.
Write to the cntlReg register the decode address for MDIO address output with the
Write-Enable mask asserted.
Poll the RDYstatus register until the MDIO write ready bit is asserted.
"1000BASE-X PCS/PMA" in Chapter 4
// EMAC Management Register 0x740 (EMAC1 Management Configuration)
// Write the data to the EMAC0 Management Configuration register to
// enable MDIO with the clock divider 0xA
mtdcr(0x0 + 13, 0x0000004A);
// Write the address of EMAC1 Management Configuration register to the
// cntlReg register
mtdcr(0x0 + 14, 0x8740);
// Poll the RDYstatus register for writing completion
while ( !(mfdcr(0x0 + 15) & 0x00000400) );
// Write the data to the PHY 0x0 register
mtdcr(0x0 + 13, 0x00001140);
// Write the decode address for MDIO Write Data to the cntlReg register
mtdcr(0x0 + 14, 0x87B0);
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for more information). MDIO must be
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
R