Xilinx Virtex-4 User Manual page 39

R
Figure 3-2
PHYEMAC#RXCLK functions as CLIENTEMAC#RXCLIENTCLKIN/2.
TIEEMAC#CONFIGVEC[65] selects between an 8-bit or 16-bit client interface.
CLIENTEMAC#RXCLIENTCLKIN
PHYEMAC#RXCLK
EMAC#CLIENTRXD[15:0]
EMAC#CLIENTRXDVLDMSW
EMAC#CLIENTRXDVLD
EMAC#CLIENTRXGOODFRAME
EMAC#CLIENTRXBADFRAME
CLIENTEMAC#RXCLIENTCLKIN
TIEEMAC#CONFIGVEC[65]
FPGA Fabric
Table 3-1
Table 3-1: Abbreviations Used in this Chapter
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
shows a block diagram of the receive client interface. In 16-bit client mode,
CLIENT
Receive
Client
Interface
Ethernet MAC Block
Figure 3-2: Receive Client Interface Block Diagram
defines the abbreviations used throughout this chapter.
Abbreviation
DA Destination address
SA Source address
L/T Length/Type field
FCS Frame check sequences
SGMII and 1000BASE-X PCS/PMA Only:
PRE Preamble
SFD Start of frame delimiter
/I1/ IDLE_1 (K28.5/D5.6)
/I2/ IDLE_2 (K28.5/D16.2)
/R/ Carrier Extend (K23.7)
/S/ Start of Packet (K27.7)
/T/ End of Packet (K29.7)
/V/ Error Propagation (K30.7)
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RX_CLK
(Internal Signal)
Receive
RX_DATA_VALID
Engine
(Internal Signal)
RX_DATA[7:0]
(Internal Signal)
RX_GOOD_FRAME
(Internal Signal)
RX_BAD_FRAME
(Internal Signal)
Definition
Client Interface
PHY
PHYEMAC#RXCLK
PHYEMAC#RXD[7:0]
PHYEMAC#RXDV
PHYEMAC#RXER
ug074_3_04_070105
Length
6 bytes
6 bytes
2 bytes
4 bytes
7 bytes
1 byte
2 bytes
2 bytes
1 byte
1 byte
1 byte
1 byte
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