Xilinx Virtex-4 User Manual page 118

Chapter 4: Physical Interface
GTX_CLK
PHYEMAC#GTXCLK
TX Client
Logic
CLIENTEMAC#TXCLIENTCLKIN
BUFG
EMAC#CLIENTTXCLIENTCLKOUT
RX Client
Logic
CLIENTEMAC#RXCLIENTCLKIN
BUFG
EMAC#CLIENTRXCLIENTCLKOUT
CLIENTEMAC#DCMLOCKED
Notes:
1) A regional buffer (BUFR) can replace this BUFG.
Refer to the Virtex-4 User Guide for BUFR usage guidelines.
An IDELAY is used to generate 2 ns of skew required between RGMII_TXC_# and
RGMII_TXD_# at the pin level. To access the IDELAY component, the
EMAC#CLIENTTXGMIIMIICLKOUT signal is routed to an unused IOB configured as an
IOBUF. The T control pin of the IOBUF is tied to ground to loop the clock back to the
IDELAY. The IDELAY setting can be used to shift the clock through the data. The output of
the IOB must not be connected to an external signal.
The EMAC#CLIENTTXCLIENTCLKOUT output port connects to the
CLIENTEMAC#TXCLIENTCLKIN input port and transmitter client logic in the FPGA
fabric through a BUFG. The receiver client clocking is similar.
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118
EMAC#
CLIENTEMAC#TXGMIIMIICLKIN
EMAC#CLIENTTXGMIIMIICLKOUT
EMAC#PHYTXD[3:0]
EMAC#PHYTXD[7:4]
PHYEMAC#MIITXCLK
PHYEMAC#RXD[3:0]
PHYEMAC#RXD[7:4]
PHYEMAC#RXCLK
Figure 4-14: Tri-Mode RGMII v2.0 Clock Management
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IDELAY
(1)
BUFG
ODDR
OBUF
D1 Q
D2
IBUF
Q1 D
Q2
DCM
1
0 CLK0
CLKIN
BUFGMUX
CLKFB
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
R
IOBUF
RGMII_IOB_#
No Connection
OBUF
RGMII_TXC_#
RGMII_TXD_#[3:0]
RGMII_RXD_#[3:0]
SPEED_IS_10_100
IBUFG
RGMII_RXC_#
UG074_3_78_031009