Xilinx Virtex-4 User Manual page 67

Fpga embedded tri-mode ethernet mac
Hide thumbs Also See for Virtex-4:
Table of Contents

Advertisement

R
TX_STATISTICS_VECTOR (bits 28 down to 20 inclusive) are only for half-duplex mode.
When operating in full-duplex mode these bits are set to a logic 0.
CLIENTEMAC#TXCLIENTCLKIN
CLIENTEMAC#TXD[7:0]
CLIENTEMAC#TXDVLD
EMAC#CLIENTTXACK
CLIENTEMAC#TXFIRSTBYTE
EMAC#CLIENTTXSTATSBYTEVLD
EMAC#CLIENTTXSTATSVLD
EMAC#CLIENTTXSTATS
Table 3-4: Bit Definitions for the Transmitter Statistics Vector
TX_STATISTICS_VECTOR
31
30
29
[28:25]
24
23
22
21
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
DA
Figure 3-34: Transmitter Statistics Vector Timing
Name
PAUSE_FRAME_TRANSMITTED
Reserved
Reserved
TX_ATTEMPTS[3:0]
Reserved
EXCESSIVE_COLLISION
LATE_COLLISION
EXCESSIVE_DEFERRAL
www.xilinx.com
SA
L/T
DATA
Description
Asserted if the previous frame was a pause frame
initiated by the Ethernet MAC in response to
asserting CLIENTEMAC#PAUSEREQ.
Undefined.
Returns a logic 0.
The number of attempts made to transmit the
previous frame. A 4-bit number where 0x0 = one
1 = two attempts, up to 0xF which
attempt; 0x
describes 16 attempts.
Returns a logic 0.
Asserted if a collision is detected on each of the
last 16 attempts to transmit the previous frame.
Asserted if a late collision occurred during frame
transmission.
Asserted if the previous frame was deferred for
an excessive amount of time as defined by the
maxDeferTime constant in the IEEE Std 802.3-
2002 specification.
Client Interface
0 1
31
ug074_3_36_080805
67

Advertisement

Table of Contents
loading

Table of Contents