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Chapter 3: Client, Host, and MDIO Interfaces
Table 3-25: DCR Ready Status Register RDYStatus (Read Only)
DCR
Offset
0
1
2
3
4
0xF
Bit
[0:16]
Reserved.
[24]
Reserved.
EMAC1 Only:
[17]
Configuration Write Ready bit.
[18]
Configuration Read Ready bit.
[19]
Address Filter Write Ready bit.
[20]
Address Filter Read Ready bit.
[21]
MDIO Write Ready bit.
[22]
MDIO Read Ready bit.
[23]
Statistics IP Read Ready bit.
EMAC0 Only:
[25]
Configuration Write Ready bit.
[26]
Configuration Read Ready bit.
[27]
Address Filter Write Ready bit.
[28]
Address Filter Read Ready bit.
[29]
MDIO Write Ready bit.
[30]
MDIO Read Ready bit.
[31]
Statistics IP Read Ready bit.
Notes:
1. For more information on Statistics IP, see
In addition to the DCRs, the DCR bus bridge contains three registers. These registers are
accessed indirectly through the DCRs.
When the interrupt method is selected to inform the host of access completion status, the
IRSTATUS register contains the interrupt request when an access is completed. When the
host services the interrupt, it reads this register to determine the type of host access
completed. Before exiting the interrupt service routine, the host writes to this register to
clear the interrupt request bit.
The IRENABLE register is programmed to allow updating of the interrupt request in the
IRSTATUS register. When an enable bit is cleared, the corresponding bit in the IRSTATUS
register is not updated. The MIIMWRDATA register temporarily holds MDIO write data
for output to the MDIO write data bus. In the case of an MDIO read, there is no need to
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86
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RESERVED
Description
(1)
(1)
"Interfacing to an FPGA Fabric-Based Statistics Block" in Chapter
www.xilinx.com
6.
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
R
Default Value
All 0s
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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