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R
Host/Tie Interface
The host/tie interfaces provide the host, or fabric, access to the control registers for the
address filter.
The tie-off interface allows the unicast address register, pause frame source address, and
address filter promiscuous mode bit to be set directly by the fabric when the FPGA is
configured. In this way, the address filter performs functions with the unicast address
without using the host interface. The TIEEMAC#UNICASTADDR[47:0] and
TIEEMAC#CONFIGVEC[47:0] should both be tied to the unicast address.
TIEEMAC#UNICASTADDR[47:0] initializes unicast address word 0 [31:0] and unicast
address word 1 [15:0] while TIEEMAC#CONFIGVEC[47:0] initializes the pause frame
source address of the receiver configuration register word 0 [31:0] and receiver
configuration register word 1[15:0]. TIEEMAC#CONFIGVEC[64] initializes the
promiscuous mode bit (bit [31] of the address filter mode register). The tie interface does
not initialize the four multicast address register values.
When the host interface is used, all the address filter registers are accessible by software,
using either the DCR bus or the generic host bus. The tie interface initialization values to
the registers can be overridden by the software through the host interface. Also, the four
multicast address registers are programmed through the host interface.
Client RX Data/Control Interface
The AF generates the EMAC#CLIENTRXFRAMEDROP signal to inform the client that the
destination MAC address of an incoming receive Ethernet frame does not match with any
of the acceptable addresses stored in the AF. This control signal is asserted regardless of
whether the AF is enabled or disabled (promiscuous mode).
Figure 3-24
(8-bit mode). The address filter is disabled in this timing diagram.
CLIENTEMAC#RXCLIENTCLKIN
EMAC#CLIENTRXDVLD
EMAC#CLIENTRXD[7:0]
EMAC#CLIENTRXGOODFRAME
EMAC#CLIENTRXFRAMEDROP
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
shows the timing diagram when a frame matches a valid location in the AF
Previous Frame
Dropped
Figure 3-24: Frame Matching Timing Diagram (8-Bit Mode)
www.xilinx.com
n–2
n–1
n
n+1 n+2 n+3 n+4 n+5 n+6 n+7
DA
Current Frame
Passed
Client Interface
SA
ug074_3_26_080805
59
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