Xilinx Virtex-4 User Manual page 116

Chapter 4: Physical Interface
Figure 4-13
the Hewlett Packard RGMII specification v2.0. GTX_CLK must be provided to the Ethernet
MAC with a high quality 125 MHz clock that satisfies the IEEE Std 802.3-2002
requirements. The EMAC#CLIENTTXGMIIMIICLKOUT output port connects to a DCM
which in turn drives the RGMII transmitter logic in the FPGA fabric and the
CLIENTEMAC#TXGMIIMIICLKIN input port. The RGMII_TXC_# is derived from the
CLK90 output of the DCM. The DCM is used to generate 2 ns of skew required between
RGMII_TXC_# and the RGMII_TXD_# at the FPGA device pads. This delay is specified in
the Hewlett Packard RGMII Specification, v2.0 to provide setup and hold time on the
external interface.
GTX_CLK
TX CLIENT
LOGIC
NC
RX CLIENT
LOGIC
NC
Notes:
1) An optional IDELAY can be used to adjust setup and hold timing.
Figure 4-13: 1 Gb/s RGMII Hewlett Packard v2.0 Clock Management
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116
shows the clock management used with the RGMII interface when following
EMAC#
PHYEMAC#GTXCLK
CLIENTEMAC#TXGMIIMIICLKIN
EMAC#CLIENTTXGMIIMIICLKOUT
CLIENTEMAC#TXCLIENTCLKIN
EMAC#CLIENTTXCLIENTCLKOUT
EMAC#PHYTXD[3:0]
EMAC#PHYTXD[7:4]
PHYEMAC#MIITXCLK
CLIENTEMAC#RXCLIENTCLKIN
EMAC#CLIENTRXCLIENTCLKOUT
PHYEMAC#RXD[3:0]
PHYEMAC#RXD[7:4]
PHYEMAC#RXCLK
CLIENTEMAC#DCMLOCKED
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DCM
BUFG
CLK0
CLKFB
CLKIN
BUFG
CLK90
ODDR
OBUF
1
D1 Q
0
D2
ODDR
OBUF
D1
Q
D2
IBUF
Q1 D
BUFG
DCM
Q2
CLK0
CLKIN
CLKFB
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
R
RGMII_TXC_#
RGMII_TXD_#[3:0]
RGMII_RXD_#[3:0]
IBUFG
RGMII_RXC_#
UG074_58_040609