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Table 4-6: 10/100/1000 SGMII and 1000BASE-X PCS/PMA Interface Signals (Cont'd)
Signal
RXNOTINTABLE_#
RXRUNDISP _#
RXCLKCORCNT[2:0]_#
SIGNAL_DETECT _#
TXBUFERR_#
CLIENTEMAC#DCMLOCKED
DADDR
DO_#
DRDY
DCLK
DI_#
DEN_#
DWE_#
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Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
10/100/1000 Serial Gigabit Media Independent Interface (SGMII)
Direction
Input
Indicates non-existent 8B/10 code.
Running disparity in the received serial data. When RXNOTINTABLE
Input
is asserted in RXDATA, this signal becomes the ninth data bit.
Input
Status denoting the occurrence of clock correction.
Signal direct from PMD sublayer indicating the presence of light
detected at the optical receiver, as defined in IEEE Std 802.3, Clause 36.
If asserted High, the optical receiver has detected light. When
Input
deasserted Low this indicates the absence of light.
If unused, this signal should be tied High to enable correct operation
the Ethernet MAC.
Input
TX buffer error (overflow or underflow).
If a DCM is used to derive any of the clock signals going to the
Ethernet MAC, the locked port of the DCM must be connected to the
CLIENTEMAC#DCMLOCKED port of the Ethernet MAC. The
Input
Ethernet MAC is held in reset until CLIENTEMAC#DCMLOCKED is
driven to logic 1.
If DCM is not used, tie this port to a logic 1.
Input
Dynamic configuration address bus.
Output
Configuration output data bus.
Output
Strobe that indicates read/write cycle is complete.
Input
Dynamic configuration bus clock.
Input
Dynamic configuration input data bus.
Input
Dynamic configuration bus enable when set to a logic 1.
Input
Dynamic configuration write enable when set to a logic 1.
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