Xilinx Virtex-4 User Manual page 165

R
Virtex-4 FPGA Embedded
Tri-Mode Ethernet MAC
CLIENTEMAC0TXCLIENTCLKIN
EMAC0CLIENTTXSTATSVLD
EMAC0CLIENTTXSTATSBYTEVLD
CLIENTEMAC0RXCLIENTCLKIN
EMAC0CLIENTRXSTATS[6:0]
EMAC0CLIENTRXSTATSVLD
EMAC0CLIENTRXSTATSBYTEVLD
CLIENTEMAC1TXCLIENTCLKIN
EMAC1CLIENTTXSTATSVLD
EMAC1CLIENTTXSTATSBYTEVLD
CLIENTEMAC1RXCLIENTCLKIN
EMAC1CLIENTRXSTATS[6:0]
EMAC1CLIENTRXSTATSVLD
EMAC1CLIENTRXSTATSBYTEVLD
DCRABUS
DCRWRITE
DCRREAD
DCRDINBUS
DCRACK
DCRRDBUS
DCRCLK
HOSTCLK
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Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
EMAC0CLIENTTXSTATS
EMAC1CLIENTTXSTATS
HOSTMIIMSEL
OR
HOSTMIIMRDY
HOSTRDDATA[15]
HOSTRDDATA[8:0]
HOSTRDDATA[9]
HOSTRDDATA[10]
HOSTWRDATA[31:0]
Figure 6-3: DCR Bus to Ethernet Statistics Connection
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Interfacing to an FPGA Fabric-Based Statistics Block
LogiCORE Ethernet Statistics
Example Design
txclientclkin
clienttxstats
clienttxstatsvld host_miim_sel
clienttxstatsbytevalid
rxclientclkin host_addr[8:0]
clienttxstatsvld[6:0] host_addr[9]
clientrxstatsvld host_rd_data[31:0]
clientrxstatsbytevalid host_stats_msw_rdy
host_stats_lsw_rdy
LogiCORE Ethernet Statistics
Example Design
txclientclkin
clienttxstats
clienttxstatsvld host_miim_sel
clienttxstatsbytevalid
rxclientclkin host_addr[8:0]
clienttxstatsvld[6:0] host_addr[9]
clientrxstatsvld host_rd_data[31:0]
clientrxstatsbytevalid host_stats_msw_rdy
host_stats_lsw_rdy
D Q
EN
NOR
DCRCLK
host_clk
host_req
OR
host_clk
host_req
OR
1
0
UG074_4_03_012408
165