Table of Contents
Advertisement
Chapter 3: Client, Host, and MDIO Interfaces
Table 3-27: Interrupt Enable Register IRENABLE
Address
Code
0
1
2
3
4
0x3A4
Bit
[0:16]
Reserved.
[17]
Configuration Write IR-enable bit.
[18]
Configuration Read IR-enable bit.
[19]
Address Filter Write IR-enable bit.
[20]
Address Filter Read IR-enable bit.
[21]
MDIO Write IR-enable bit.
[22]
MDIO Read IR-enable bit.
[23]
Statistics IP Read IR-enable bit.
[24]
Reserved
[25]
Configuration Write IR-enable bit.
[26]
Configuration Read IR-enable bit.
[27]
Address Filter Write IR-enable bit.
[28]
Address Filter Read IR-enable bit.
[29]
MDIO Write IR-enable bit.
[30]
MDIO Read IR-enable bit.
[31]
Statistics IP Read IR enable bit.
Notes:
1. For more information on Statistics IP, see
Table 3-28: Host Interface MDIO Write Data Register (MIIMWRDATA)
Address
Code
0
1
2
3
4
0x3B0
Bit
[0:15]
Reserved.
[16:31]
Data- temporarily holds MDIO write data for output onto the host write data bus.
Notes:
1. See
"Interfacing to an FPGA Fabric-Based Statistics Block" in Chapter
www.BDTIC.com/XILINX
88
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RESERVED
Description
(1)
(1)
"Interfacing to an FPGA Fabric-Based Statistics Block" in Chapter
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RESERVED
Description
www.xilinx.com
Ethernet MAC
EMAC1
EMAC1
EMAC1
EMAC1
EMAC1
EMAC1
EMAC1
EMAC0
EMAC0
EMAC0
EMAC0
EMAC0
EMAC0
EMAC0
MIIMWRDATA
6.
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
R
Default Value
–
0
0
0
0
0
0
0
0
–
0
0
0
0
0
0
0
0
6.
Default Value
All 0s
undefined
Advertisement
Table of Contents
