Xilinx Virtex-4 User Manual page 109

R
Tri-Mode Operation
Figure 4-9
must be provided to the Ethernet MAC with a high quality 125 MHz clock that satisfies the
IEEE Std 802.3-2002 requirements.
CLIENTEMAC#TXGMIIMIICLKIN, PHYEMAC#MIITXCLK, and the GMII transmit
registers are all clocked by a BUFGMUX. This mux selects GTX_CLK when the speed is
1 Gb/s, and MII_TX_CLK_# when the speed of operation is 10 or 100 Mb/s.The
EMAC#CLIENTTXCLIENTCLKOUT output port connects to the
CLIENTEMAC#TXCLIENTCLKIN input port and transmit client logic in the FPGA fabric
through a BUFG. The receive client clocking is similar.
The GMII_RX_CLK_# generated from the PHY has a frequency of either 2.5 MHz, 25 MHz
or 125 MHz, depending on the operating speed of the Ethernet MAC. The
CLIENTEMAC#DCMLOCKED port must be tied High.
A DCM must be used on the GMII_RX_CLK_# clock path as illustrated in
meet the GMII input setup and hold requirements when operating at 1 Gb/s. Phase
shifting may then be applied to the DCM to fine tune the setup and hold times of the input
GMII receiver signals which are sampled at the GMII IOB input flip-flops.
When operating at 10 Mb/s and 100 Mb/s, the DCM is bypassed and held in reset. This is
achieved using the BUFGMUX global clock multiplexer shown in
requirement to bypass the DCM because the clock frequency of GMII_RX_CLK_# is
2.5 MHz when operating at 10 Mb/s and 2.5 MHz is below the DCM low frequency
threshold for Virtex®-4 FPGAs. However, at the 10 Mb/s and 100 Mb/s operating speeds,
input setup and hold margins increase appropriately and the input MII data can be
sampled correctly without use of the DCM.
The GMII_TX_CLK_# is derived from the Ethernet MAC, routed through an OBUF, and
then connected to the PHY. Since GMII_TX_CLK_# is derived from
EMAC#CLIENTTXGMIIMIICLKOUT or MII_TX_CLK_#, its frequency automatically
changes between 125 MHz, 25 MHz, or 2.5 MHz depending on the speed setting of the
Ethernet MAC.
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Gigabit Media Independent Interface (GMII) Signals
shows the clock management used with the tri-mode GMII interface. GTX_CLK
www.xilinx.com
Figure 4-9 to
Figure 4-9. It is a
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