Xilinx Virtex-4 User Manual page 66

Chapter 3: Client, Host, and MDIO Interfaces
The TX_STATISTICS_VECTOR is a 32-bit wide vector and is internal in the transmit
engine. This vector is muxed out to a one-bit signal, EMAC#CLIENTTXSTATS, as shown in
Figure
CLIENTEMAC#TXCLIENTCLKIN
TX_STATISTICS_VALID
(internal signal)
TX_STATISTICS_VECTOR[31:0]
(internal signal)
EMAC#CLIENTTXSTATSVLD
EMAC#CLIENTTXSTATS
The block diagram for the transmitter statistics mux in the Ethernet MAC is shown in
Figure
All bit fields in EMAC#CLIENTTXSTATS are only valid when the
EMAC#CLIENTTXSTATSVLD is asserted as illustrated in
EMAC#CLIENTTXSTATSBYTEVLD is asserted if an Ethernet MAC frame byte (DA to FCS
inclusive) is being transmitted. The signal is valid on every
CLIENTEMAC#TXCLIENTCLKIN cycle.
www.BDTIC.com/XILINX
66
3-32.
0 1 2
Figure 3-32: Transmitter Statistics Mux Timing
3-33.
TX_STATISTICS_VECTOR[31:0]
CLIENTEMAC#TXCLIENTCLKIN
EMAC#CLIENTTXSTATSBYTEVLD
CLIENTEMAC#TXCLIENTCLKIN
CLIENTEMAC#TXCLIENTCLKIN
Figure 3-33: Transmitter Statistics Mux Block Diagram
www.xilinx.com
3 4 5
Ethernet MAC
(Internal Signal)
[31:0]
TXSTATSMUX
EMAC#CLIENTTXSTATS
TXSTATSDEMUX
RESET
TXSTATSVEC[31:0]
User Defined
Statistics Processing Block
Embedded Tri-Mode Ethernet MAC User Guide
28 29 30 31
UG074_03_34_080805
TX_STATISTICS_VALID
(Internal Signal)
Ethernet MAC Block
FPGA Fabric
EMAC#CLIENTTXSTATSVLD
TXSTATSVLD
ug074_3_35_080805
Figure 3-34.
UG074 (v2.2) February 22, 2010
R