Xilinx Virtex-4 User Manual page 50

Chapter 3: Client, Host, and MDIO Interfaces
Figure 3-13
Figure 3-14
CLIENTEMAC#TXCLIENTCLKIN
PHYEMAC#MIITXCLK
(CLIENTEMAC#TXCLIENTCLKIN/2)
CLIENTEMAC#TXD[15:0]
CLIENTEMAC#TXDVLD
CLIENTEMAC#TXDVLDMSW
EMAC#CLIENTTXACK
CLIENTEMAC#TXFIRSTBYTE
CLIENTEMAC#TXUNDERRUN
EMAC#CLIENTTXCOLLISION
EMAC#CLIENTTXRETRANSMIT
Figure 3-13: 16-Bit Transmit Back-to-Back Transfer (Even Byte Case)
CLIENTEMAC#TXCLIENTCLKIN
PHYEMAC#MIITXCLK
(CLIENTEMAC#TXCLIENTCLKIN/2)
CLIENTEMAC#TXD[15:0]
CLIENTEMAC#TXDVLD
CLIENTEMAC#TXDVLDMSW
EMAC#CLIENTTXACK
CLIENTEMAC#TXFIRSTBYTE
CLIENTEMAC#TXUNDERRUN
EMAC#CLIENTTXCOLLISION
EMAC#CLIENTTXRETRANSMIT
Figure 3-14: 16-Bit Transmit Back-to-Back Transfer (Odd Byte Case)
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50
shows the timing diagram for 16-bit transmit for an even-byte case, and
shows the timing diagram for an odd-byte case.
D(n-2), D(n-3) D(n), D(n-1)
1st Frame
0xXX, D(n)
D(n-1), D(n-2)
1st Frame
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DA1, DA0
IFG 2nd Frame
DA1, DA0
IFG 2nd Frame
Embedded Tri-Mode Ethernet MAC User Guide
DA3, DA2 DA5, DA4
ug074_3_15_101004
DA3, DA2 DA5, DA4
ug074_3_16_101004
UG074 (v2.2) February 22, 2010
R