Xilinx Virtex-4 User Manual page 73

R
Figure 3-39
HOSTOPCODE[1:0]
HOSTREQ
HOSTWRDATA[31:0]
HOSTRDDATA[31:0]
HOSTMIIMRDY
HOSTCLK
HOSTMIIMSEL
HOSTADDR[9:0]
HOSTEMAC1SEL
DCREMACENABLE
DCRHOSTDONEIR
Generic Host Bus
When the generic host bus is used, the HOSTEMAC1SEL signal selects between the host
access of EMAC0 or EMAC1. When HOSTEMAC1SEL is asserted, the host accesses
EMAC1. If only one Ethernet MAC is used, this signal can be tied-off to use either one of
the Ethernet MACs.
To use the DCR bus for the host interface, the DCREMACENABLE signal is asserted.
Because the DCREMACENABLE signal is input from the fabric, it can be tied-off to select
between the DCR bus or the generic host bus during the FPGA power-up configuration.
When using the PowerPC processor and its DCR bus interface to control the Ethernet MAC
registers, either connect the EMAC DCREMACENABLE port to the PPC405
DCREMACENABLER port or assert the DCREMACENABLE input to the EMAC.
The PowerPC processor serves as host processor when a DCR bus is used. Interrupt
request is one of the methods used by the PowerPC processor to determine when the host
interface completes a DCR host access command.
The interrupt request DCRHOSTDONEIR signal is only active when the DCR bus is used,
and the host interface register IRENABLE is programmed to enable interrupt. This signal is
active High and level sensitive. When a host access through the DCR bus is completed, the
DCRHOSTDONEIR signal is asserted. The host needs to service the interrupt request and
clear the host interface register (IRSTATUS) to deassert this signal. See
as the Host Bus," page 83
Access to the management interface depends on the type of transaction.
the access method required for each transaction type.
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
shows the block diagram of the host interface.
DCR Bus
(Connected internally
to PowerPC)
Ethernet MAC Block
FPGA Fabric
Figure 3-39: Ethernet MAC Host Interface Block Diagram
for a description of the DCR.
www.xilinx.com
MIIMSEL0
REQ0
OPCODE0
ADDR0
WRD0
MIIMRDY0
RDD0
Host Interface
(All internal signals)
MIIMSEL1
REQ1
OPCODE1
ADDR1
WRD1
MIIMRDY1
RDD1
Host Interface
EMAC0
EMAC1
ug074_3_41_080805
"Using the DCR Bus
Table 3-6 shows
73