Xilinx Virtex-4 User Manual page 103

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data rate at the Ethernet MAC input. The clock enables for the client logic are provided by
the output of another toggle flip-flop clocked on the rising edge of the MII clock.
Figure 4-4
EMAC#CLIENTTXGMIIMIICLKOUT
PHYEMAC#RXCLK
Clock Enable
EMAC#PHYTXD
PHYEMAC#RXD
CLIENTEMAC#TXCLIENTCLKIN
CLIENTEMAC#RXCLIENTCLKIN
The MII clock has a period of 40 ns at 100 Mb/s and 400 ns at 10 Mb/s. Since the client and
MII logic are constrained to run at 1 Gb/s (125 MHz), the data will be stable 8 ns after the
rising clock edge. This gives a window of 32 ns at 100 Mb/s for the data to be sampled into
the Ethernet MAC. As the client clock is derived on the falling edge of the MII clock the
data is clocked into the MAC at least 12 ns after the data is stable.
Using this technique the EMAC#CLIENTTXACK signal must be registered at the output of
the Ethernet MAC. EMAC#CLIENTTXACK is generated on the rising edge of the client
clock input CLIENTEMAC#TXCLIENTCLKIN and sampled by the client logic on the
rising edge of the MII clock. This technique can lead to the first byte of data being removed
from the client transmitter bus too soon. However, if the EMAC#CLIENTTXACK signal is
registered on the MII clock (and clock enabled like the rest of the client logic), the data
removal problem will not happen.
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
shows the timing of a data transfer over the client interface.
40 ns (or 400 ns)
12 ns (or 192 ns)
8 ns
Figure 4-4: Client Interface Timing
Figure 4-5
www.xilinx.com
Media Independent Interface (MII)
illustrates the timing diagram.
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