Xilinx Virtex-4 User Manual page 102

Chapter 4: Physical Interface
TX Client
Logic
TX_ACK
Registered
CE
RX Client
Logic
CE
Using the example in
These outputs run at 25 MHz at 100 Mb/s and 2.5 MHz at 10 Mb/s, or twice as fast as the
client clock inputs. To produce the correct clock frequency on these inputs, the MII clocks
are put through a toggle flip-flop (clocked on the falling edge of the MII clock) and routed
to the client clock inputs. The client logic must also be clock enabled to achieve the correct
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102
EMAC#
PHYEMAC#GTXCLK
GND
CLIENTEMAC#TXGMIIMIICLKIN
EMAC#PHYTXD[3:0]
CLIENTEMAC#TXCLIENTCLKIN
EMAC#CLIENTTXCLIENTCLKOUT
NC
PHYEMAC#MIITXCLK
CLIENTEMAC#RXCLIENTCLKIN
EMAC#CLIENTRXCLIENTCLKOUT
NC
PHYEMAC#RXCLK
PHYEMAC#RXD[3:0]
Figure 4-3: MII Clock Management with Clock Enable
Figure
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D Q
D
D
Q D
D
D
4-3, all logic is now clocked on the MII interface clock outputs.
Embedded Tri-Mode Ethernet MAC User Guide
Q
OBUF
MII_TXD_#[3:0]
Q
BUFG
MII_TX_CLK_#
BUFG IBUFG
MII_RX_CLK_#
MII_RXD_#[3:0]
IBUF
Q
Q
UG074_3_68_032207
UG074 (v2.2) February 22, 2010
R