Xilinx Virtex-4 User Manual page 158

Chapter 6: Use Models
Reading From the Statistics IP Register (When Implemented in the Fabric)
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2.
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Assuming the DCR base address is 0x0, to read from EMAC0 statistics IP register 0x0:
Reading from the Multicast Address Table Register of the Address Filter
Block
The same methods used in reading and writing to the Ethernet MAC configuration
registers through the DCR apply to the address filter configuration registers.
1.
2.
3.
4.
Assuming the DCR base address is 0x0, to read from the multicast address table register
(2) of EMAC0:
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158
Write to cntlReg register with the desired address of the statistics IP register.
Poll the RDYstatus register until the statistics Read-Ready bit is asserted.
Read from the dataRegMSW and dataRegLSW registers to show the value from the
statistics IP register.
// Statistics IP Register 0x0 (Check how many frames were received OK)
//
Write the address of the Statistics IP register to the cntlReg register
mtdcr(0x0 + 14, 0x0);
// Poll the RDYstatus register
while ( !(mfdcr(0x0 + 15) & 0x00000001) );
// Read the values returned of the Statistics IP Register 0x0 (64-bit
// value)from the dataRegMSW and dataRegLSW registers
stats_msw = mfdcr(0x0 + 12);
stats_lsw = mfdcr(0x0 + 13);
Write to dataRegLSW register the read mask bit to read the multicast address table
register with the respective register being accessed (there are four multicast address
table registers in the address filter block).
Write to cntlReg register with the address register of multicast address - 0x38C for
EMAC0 and 0x78C for EMAC1. Set the Write enable bit to write to the multicast
address (Word 1) (see Table
Poll the RDYstatus register until the address filter read-ready bit is asserted.
Read from the dataRegMSW and dataRegLSW registers to show the address stored in
the multicast address table register selected for reading.
// MULTI_ADDR Register 2 of AF Block
// Set the enable bit of the MULTI_ADDR RNW and MULTI_ADDR Register 2
mtdcr(0x0 + 13, 0x00820000);
// Write the address of EMAC0 Multicast Address register to the cntlReg
// register
mtdcr(0x0 + 14, 0x838C);
// Poll the RDYstatus register
while ( !(mfdcr(0x0 + 15) & 0x00000008) );
// Read the values returned of the Multicast Address Word0 and Word1
// registers (48-bit value)
// from the dataRegMSW and dataRegLSW registers
mult_addr_msw = mfdcr (0x0 + 12);
mult_addr_lsw = mfdcr (0x0 + 13);
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3-19, "Multicast Address Table Access (Word
Embedded Tri-Mode Ethernet MAC User Guide
1)").
UG074 (v2.2) February 22, 2010
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