Xilinx Virtex-4 User Manual page 46

Fpga embedded tri-mode ethernet mac
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Chapter 3: Client, Host, and MDIO Interfaces
CLIENTEMAC#TXCLIENTCLKIN
CLIENTEMAC#TXD[7:0]
CLIENTEMAC#TXDVLD
EMAC#CLIENTTXACK
CLIENTEMAC#TXFIRSTBYTE
CLIENTEMAC#TXUNDERRUN
EMAC#CLIENTTXCOLLISION
EMAC#CLIENTTXRETRANSMIT
Figure 3-9: Collision Handling - No Frame Retransmission Required
IFG Adjustment
The length of the IFG can be varied in full-duplex mode. If this function is selected (using
a configuration bit in the transmitter control register, see
page
frame, until the requested number of idle cycles has elapsed. The number of idle cycles is
controlled by the value on the CLIENTEMAC#TXIFGDELAY port at the start-of-frame
transmission.
In full-duplex configurations, the minimum IFG is 12 bytes (96 bit times). In half-duplex
configurations, the minimum supported IFG is 18 bytes (144 bit times) when using the MII
physical interface, or 26 bytes (208 bit times) when using the RGMII physical interface.
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46
If the EMAC#CLIENTTXRETRANSMIT signal is 0 in the same clock cycle when the
EMAC#CLIENTTXCOLLISION signal is
exceeded the Ethernet specification, and the frame should be dropped by the client.
The client can then make any new frame available to the Ethernet MAC for
transmission without timing restriction. This process is shown in
74), then the Ethernet MAC exerts back pressure to delay the transmission of the next
Figure 3-10
shows the Ethernet MAC operating in this mode.
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, the number of retries for this frame has
1
Figure
"Configuration Registers,"
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
R
3-9.
ug074_3_11_101004

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