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R
GTX_CLK
PHYEMAC#GTXCLK
TX Client
Logic
CLIENTEMAC#TXCLIENTCLKIN
BUFG
EMAC#CLIENTTXCLIENTCLKOUT
RX Client
Logic
CLIENTEMAC#RXCLIENTCLKIN
BUFG
EMAC#CLIENTRXCLIENTCLKOUT
CLIENTEMAC#DCMLOCKED
Notes:
1) A regional buffer (BUFR) can replace this BUFG.
Refer to the Virtex-4 User Guide for BUFR usage guidelines.
Figure 4-15: Alternative Tri-Mode RGMII v2.0 Clock Management
The CLIENTEMAC#DCMLOCKED port must be tied HIGH. The RGMII_RXC_# is
generated from the PHY and connected to the PHYEMAC#RXCLK pin and receive logic
through a DCM and a BUFG. A DCM must be used on the RGMII_RXC_# clock path as
illustrated in
1 Gb/s. Phase shifting may then be applied to the DCM to fine-tune the setup and hold
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
V
CC
GND
SPEED_IS_10_100
V
CC
1
0
GND
V
CC
0
1
GND
EMAC#
CLIENTEMAC#TXGMIIMIICLKIN
EMAC#CLIENTTXGMIIMIICLKOUT
EMAC#PHYTXD[3:0]
EMAC#PHYTXD[7:4]
PHYEMAC#MIITXCLK
PHYEMAC#RXD[3:0]
PHYEMAC#RXD[7:4]
PHYEMAC#RXCLK
Figure 4-14
to meet the RGMII 1 ns setup and 1 ns hold requirements at
www.xilinx.com
D1
D2
ODDR
D1
Q
D2
D1
D2
IDELAY
(1)
BUFG
ODDR
D1
Q
D2
Q1
D
Q2
1
0
BUFGMUX
10/100/1000 RGMII
IOBUF
RGMII_IOB_#
No Connection
OBUF
RGMII_TXC_#
OBUF
RGMII_TXD_#[3:0]
IBUF
RGMII_RXD
_#
[3:0]
SPEED_IS_10_100
DCM
IBUFG
CLK0
CLKIN
RGMII_RXC_#
CLKFB
UG074_3_79_031009
119
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