Xilinx Virtex-4 User Manual page 5

Date Version
11/11/06 1.5 • Book restructuring of Chapter 3 content:
• Globally changed all instances of PHYEMAC#TXD to EMAC#PHYTXD.
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• Updated/corrected
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• Corrected section
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03/27/07 1.6 •
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www.BDTIC.com/XILINX
UG074 (v2.2) February 22, 2010
•
Sections on Host, Client, and MDIO interfaces remain in
and MDIO Interfaces."
• Pulled out section on Physical Interface to new
•
Pulled out sections on Clock Frequency Support, Ethernet MAC Configuration, and Auto-
Negotiation Interrupt to new
"Features" in Chapter
Table 3-30: Added EMAC1 registers IRSTATUS, IRENABLE, MIIMWRDATA, and
MIIMCNTL.
Figure
"SGMII RX Elastic Buffer"
"1 Gb/s RGMII Clock Management" in Chapter
"10/100/1000 SGMII Clock Management" in Chapter 4:
reference clock for the RocketIO transceiver changed from 125 MHz to 250 MHz. The GT11
clock schemes are simplified as shown in
"1000BASE-X PCS/PMA (8-bit Data Client) Clock Management" in Chapter 4:
GT11 clock schemes are simplified as shown in
"1000BASE-X PCS/PMA Clock Management" in Chapter
quality reference clock for the 16-bit Data Client MGT changed from 125 MHz to 250 MHz.
The GT11 clock schemes are simplified as shown in
Table 4-13: Corrected 4.8:7 Pause, 10 and 11 (reversed)
"MGT Elastic Buffer (Ring Buffer)" in Chapter
marks, and as a result corrected maximum frame size
"Transmit Clocking Scheme" in Chapter
generate client-side clock.
"Reading the PHY Registers Using MDIO" in Chapter
"Writing to the PHY Registers Using MDIO" in Chapter
address for EMAC1 Management Configuration; corrected decode address.
Chapter 7, "Using the Embedded Ethernet MAC"
Table 2-9: Removed Note (1).
Table 2-11: Revised Note (1).
Table 3-5: Removed exception from description of Length/Type Out of Range.
Table 3-20: Corrected default value for bit 31 (Promiscuous Mode Enable).
Chapter 4: Multiple revisions in block schematic diagram figures.
Chapter 4: Former section "1000BASE-X PCS/PMA (8-bit Data Client) Clock Management"
in Chapter 4 incorporated into section
Table 4-3: Consolidated "RISING" and "FALLING" RGMII signals into single signals with
revised descriptions. Added Note (1) to RGMII_TX_CTL_# and RGMII_RX_CTL_#.
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Revision
Chapter 4, "Physical Interface."
Chapter 5, "Miscellaneous Functions."
1: Added full-duplex qualifier for SGMII support.
3-48, Figure 4-1, Figure 4-3,
added to Chapter 4, "Physical Interface."
Figure 4-24.
Figure
Figure
5: Corrected description of inputs used to
updated.
"8-Bit Data Client."
Embedded Tri-Mode Ethernet MAC User Guide
Chapter 3, now called "Client, Host,
Figure 4-22, and Figure 4-24.
4.
The external, high-quality
4-27.
4: The external, high-
4-28.
4: Corrected underflow/overflow
(Table 4-4).
6: Corrected decode address.
6: Corrected register
The