Xilinx Virtex-4 User Manual page 31

R
Table 2-11: MAC Configuration Pins (Cont'd)
Signal
TIEEMAC#CONFIGVEC[53:0] — Configures the receive engine of the Ethernet MAC.
TIEEMAC#CONFIGVEC[53]
TIEEMAC#CONFIGVEC[52]
TIEEMAC#CONFIGVEC[51]
TIEEMAC#CONFIGVEC[50]
TIEEMAC#CONFIGVEC[49]
TIEEMAC#CONFIGVEC[48]
TIEEMAC#CONFIGVEC[47:0]
Notes:
1. A reset is needed before changes on TIEEMAC#CONFIGVEC[73] and [70:64] take effect.
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Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Direction
Receiver Reset. When this bit is
Input
This signal is an input to the reset circuit for the receiver block.
Receiver Jumbo Frame Enable. When this bit is 0, the receiver
does not pass frames longer than the maximum legal frame size
Input
specified in IEEE Std 802.3-2002. When this bit is
does not have an upper limit on frame size.
Receiver In-band FCS Enable. When this bit is
MAC receiver passes the FCS field up to the client. When this bit
Input
is 0, the Ethernet MAC receiver does not pass the FCS field. In
both cases, the FCS field are verified on the frame.
Receiver Enable. When this bit is
Input operational. When this bit is 0, the block ignores activity on the
physical interface RX port.
Receiver VLAN Enable. When this bit is
Input
are accepted by the receiver.
Receiver Half Duplex. When this bit is
Input half-duplex mode. When this bit is 0, the receiver operates in full-
duplex mode.
Pause frame Ethernet MAC Source Address[47:0]. This address is
used by the Ethernet MAC to match against the destination
address of any incoming flow control frames, and as the source
address for any outbound flow control frames.
The address is ordered for the least significant byte in the register
Input
to have the first byte transmitted or received; for example, an
Ethernet MAC address of AA-BB-CC-DD-EE-FF is stored in byte
[47:0] as 0xFFEEDDCCBBAA.
Tied to the same Ethernet MAC address as
TIEEMAC#UNICASTADDR[47:0].
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Ethernet MAC Signal Descriptions
Description
the receiver is held in reset.
1,
the receiver
1,
the Ethernet
1,
the receiver block is
1,
VLAN tagged frames
1,
the receiver operates in
1,
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