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R
Shim
Because of small differences in the way the Virtex-II Pro and Virtex-4 FPGA RocketIO
transceivers output the clock correction status and data when RXNOTINTABLE is
asserted, a shim is needed to modify the received data from the Virtex-4 FPGA RocketIO
transceiver (GT11) to the format that the EMAC is expecting.
this shim created by the CORE Generator tool for the SGMII and 1000BASE-X designs.
Table 4-9: Shim Port Names
1000BASE-X PCS/PMA Clock Management
8-Bit Data Client
Figure 4-27
and an 8-bit data client. At a line rate of 1.25 Gb/s or below, oversampling is used by the
built-in MGT digital receiver to recover clock and data. See Chapter 3 of UG076, Virtex-4
RocketIO Multi-Gigabit Transceiver User Guide for more details about the digital receiver
oversampling operation. The inputs of the GT11CLK_MGT primitive are connected to an
external, high-quality reference clock with a frequency of 250 MHz specifically for the
MGT. The output SYNCLKOUT connects to the PLL reference clock input REFCLK.
TXOUTCLK1, derived from the transmitter PLL, reflects the reference clock and drives the
other clock inputs. It connects through a global buffer to PHYEMAC#GTXCLK and into
TXUSRCLK2 and RXUSRCLK2. TXUSRCLK and RXUSRCLK are not used and are tied to
ground.
To ensure that the Ethernet MAC does not operate until the MGT has achieved all
necessary locks, the CLIENTEMAC#DCMLOCKED input signal to the EMAC# block is
generated using the TXLOCK and RXLOCK signals from the MGT, and the DCM
LOCKED output. Refer to the CORE Generator Ethernet MAC wrapper for the actual
implementation of this combined lock signal.
The EMAC#CLIENTTXCLIENTCLKOUT output port must be connected to a BUFG to
drive the transmit client logic in the FPGA fabric, and then is routed back into the input
port CLIENTEMAC#TXCLIENTCLKIN. This method is also used for the receive client
logic.
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Port Name
rxusrclk2
Rxstatus
Rxnotintable
rxd_in
rxcharisk_in
rxrundisp_in
Rxclkcorcnt
rxd_out
rxcharisk_out
rxrundisp_out
shows the clock management used with the 1000BASE-X PCS/PMA interface
www.xilinx.com
I/O
Width
I
1
Logic Clock.
I
6
Status from GT11.
I
1
Status from GT11.
I
8
Data from GT11.
I
1
Control from GT11.
I
1
Status from GT11.
O
3
Status in GT format.
Data in GT format when rxnotintable
O
8
asserted.
O
1
Control in GT/GT11 format.
O
1
Control in GT/GT11 format.
1000BASE-X PCS/PMA
Table 4-9
shows the ports of
Description
137
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