Xilinx Virtex-4 User Manual page 33

R
Table 2-14: PHY Data and Control Signals
Signal
PHYEMAC#MIITXCLK
EMAC#PHYTXCLK
EMAC#CLIENTTXGMIIMIICLKOUT
EMAC#PHYTXEN
EMAC#PHYTXER
EMAC#PHYTXD[7:0]
PHYEMAC#RXCLK
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Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Direction Mode
10/100 MII
16-bit client
Input
interface
used in
1000BASE-X
PCS/PMA
Output GMII
GMII
Output
RGMII
10/100 MII
Output GMII
RGMII
10/100 MII
GMII
Output
RGMII
10/100 MII
GMII
Output
RGMII
SGMII
1000BASE-X
10/100 MII
GMII
RGMII
Input
16-bit client
interface
used in
1000BASE-X
PCS/PMA
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Ethernet MAC Signal Descriptions
Description
The TX clock generated from the PHY when
operating in 10/100 MII mode.
When the transmit client interface is configured
to be 16 bits wide, this is the clock input port for
the CLIENTEMAC#TXCLIENTCLKIN/2. See
"Transmit (TX) Client – 16-bit Wide Interface" in
Chapter 3.
The TX clock out to the PHY in GMII 1000 Mb/s
mode only.
The TX clock out to the PHY for GMII tri-speed
mode operation and RGMII.
The data enable control signal to the PHY.
The RGMII_TX_CTL_RISING signal to the PHY.
The error control signal to the PHY.
The RGMII_TX_CTL_FALLING signal to the
PHY.
EMAC#PHYTXD[3:0] is the transmit data signal
to the PHY. EMAC#PHYTXD[7:4] are driven
Low.
The transmit data signal to the PHY.
EMAC#PHYTXD[3:0] is the
RGMII_TXD_RISING and EMAC#PHYTXD[7:4]
is the RGMII_TXD_FALLING signal to the PHY.
The TX_DATA signal to the MGT.
The recovered clock from received data stream
by the PHY.
When the receive client interface is configured to
be 16 bits wide, this signal is the clock input port
for the CLIENTEMAC#RXCLIENTCLKIN/2.
See "Receive (RX) Client – 16-bit Wide Interface"
in Chapter 3.
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