Xilinx Virtex-4 User Manual page 90

Chapter 3: Client, Host, and MDIO Interfaces
EMACISEL bit. All writes to Ethernet MAC registers are accomplished in a single host
clock cycle except for the MDIO registers.
To read data from an Ethernet MAC register through the DCR bus, the DCR cntlReg is
programmed for read, EMAC0 or EMAC1 select, and the address code. The Ethernet MAC
address code is translated and output from the host interface on the address bus
ADDR#[9:0].
The decode of the address code generates the control signals MIIMSEL#, REQ#, and
OPCODE#[1:0] that are output to the selected Ethernet MAC. The data read out from the
Ethernet MAC is deposited in DCR dataRegLSW and dataRegMSW (in the case of an
address filter or statistics IP register read) in the host interface.
Reading the configuration registers for the Ethernet MAC and the address filter registers
takes a single host clock cycle, while reading from the Ethernet MAC statistics IP registers
and MDIO registers takes multiple host clock cycles. An Ethernet MAC statistics IP register
read takes six host clock cycles. MDIO registers reads take a multiple number of host clock
cycles depending on the physical interface device. To write to any of the PCS layer registers
("Management Registers," page
register shown in
to the DCR dataRegLSW register. The mapping is shown in
0
0x1
Figure 3-45: MDIO Address Register to Access PCS Sublayer Register Block
The DCR bridge runs at the same clock frequency as the PowerPC processor. Because the
host bus is not a high performance bus, HOSTCLK runs at a lower frequency. The
HOSTCLK frequency must be an integer divide of the DCR clock frequency, and the two
clocks must be phase aligned. The DCR bridge ignores any new DCR command in the
DCR clock domain until a host access in the HOSTCLK domain is complete. Hence, the
PowerPC processor must determine when a host access is complete.
If the interrupt request method is selected, the host interface interrupt request output pin
DCRHOSTDONEIR is used to notify the host when an access is completed. In the case of a
read, when the host services the interrupt, it must issue DCR reads to dataRegLSW and
dataRegMSW to read out the Ethernet MAC register data.
The interrupt request register is located in the IRSTATUS register (Address Code 0x3A0).
After servicing the interrupt request, the host must clear the interrupt request. In addition,
the DCR RDYstatus register is provided to indicate when a multiple-cycle access is ready.
This register is allows the host to use the polling method for accesses requiring only a few
multiple host clock cycles.
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90
Figure 3-44. The PHY address and PCS register number are then written
22 26 27 31
PHY_ADDR REG_ADDR
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140), the data must be written to the MDIO Write Data
PCS Sublayer Managed Register Block
15
Control Register
0
1 Status Register
PHY Identifier Register
2
PHY Identifier Register
3
Auto-Negotiation Advertisement Register
4
Embedded Tri-Mode Ethernet MAC User Guide
Figure 3-45.
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UG074 (v2.2) February 22, 2010
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0