Xilinx Virtex-4 User Manual page 146

Fpga embedded tri-mode ethernet mac
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Chapter 4: Physical Interface
Table 4-18: Extended Status Register (Register 15) (Cont'd)
Bit(s)
Name
1000BASE-T
15.12
Half Duplex
15:11:0
Reserved
Table 4-19: Vendor-Specific Register: Auto-Negotiation Interrupt Control Register (Register 16)
Bit(s)
Name
16.15:2 Reserved
16.1
Interrupt Status
16.0
Interrupt Enable
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146
Description
The Ethernet MAC always returns a 0
for this bit because 1000BASE-T half
duplex is not supported.
Always returns 0s.
Description
Always returns 0s.
1 = Interrupt is asserted.
0 = Interrupt is not asserted.
If the interrupt is enabled, this bit is
asserted upon the completion of an
auto-negotiation cycle; it can only be
cleared by writing 0 to this bit.
If the interrupt is disabled, this bit is set
to 0.
The EMAC#CLIENTANINTERRUPT
port is wired to this bit.
1 = Interrupt is enabled.
0 = Interrupt is disabled.
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Attributes
Default Value
Returns 0
Returns 0s
000000000000
Attributes
Default Value
Returns 0s
00000000000000
Read/Write
Read/Write
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
R
0
0
1

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