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R
Figure 3-42
The five address filter registers and the contents of the registers are shown in
through
Table 3-16: Unicast Address (Word 0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0x380
Bit
Unicast Address [31:0]. This address is used to match the
[31:0]
Ethernet MAC against the destination address of any
incoming frames.
Table 3-17: Unicast Address (Word 1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0x384
Bit
[15:0]
Unicast Address [47:32].
[31:16]
Reserved.
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
shows the multicast address table memory diagram.
Multicast Address Table Access (Word 1)
HOST_ADDR
31
23
0x38C/0x78C
47
00
01
10
11
Figure 3-42: Multicast Address Table Memory Diagram.
Table
3-20.
UNICAST_ADDRESS[31:0]
Description
RESERVED
Description
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17
16 15
ADDR
MULTICAST_ADDRESS[47:32]
Multicast Address Table
Multicast Address Register 0
Multicast Address Register 1
Multicast Address Register 2
Multicast Address Register 3
9
Default Value
TIEEMAC#UNICASTADDR[31:0]
9
UNICAST_ADDRESS[47:32]
Default Value
TIEEMAC#UNICASTADDR[47:32]
Host Interface
0
0
ug074_3_44_080805
Table 3-16
8
7
6
5
4
3
2
1
R/W
R/W
8
7
6
5
4
3
2
1
R/W
R/W
–
0
0
81
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