Xilinx Virtex-4 User Manual page 82

Fpga embedded tri-mode ethernet mac
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Chapter 3: Client, Host, and MDIO Interfaces
Table 3-18: Multicast Address Table Access (Word 0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0x388
Bit
Multicast Address [31:0]. The multicast address bits [31:0] are temporarily
[31:0]
deposited into this register for writing into a multicast address register.
Table 3-19: Multicast Address Table Access (Word 1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
0x38c
Bit
Multicast Address [47:32]. The multicast address bits [47:32] are temporarily
[15:0]
deposited into this register for writing into a multicast address register.
Multicast Address: This 2-bit vector is used to choose the multicast address
register to access.
00 = Multicast Address Register 0
[17:16]
01 = Multicast Address Register 1
10 = Multicast Address Register 2
11 = Multicast Address Register 3
[22:18]
Reserved.
Multicast address read enable (RNW): When this bit is 1, a multicast address
[23]
register is read. When this bit is 0, a multicast address register is written with
the address set in the multicast address table register.
[31:24]
Reserved.
Table 3-20: Address Filter Mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0x390
Bit
[30:0]
Reserved.
Promiscuous Mode enable: When this bit is 1, the Address Filter
[31]
block is disabled. When this bit is 0, the Address Filter block is
enabled.
A timing diagram for writing to the Address Filter Registers is the same as the one shown
for writing to the Ethernet MAC Configuration Registers
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82
MULTICAST_ADDRESS[31:0]
Description
RESERVED
Description
RESERVED
Description
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9
8
7
6
5
Default Value
All 0s
9
8
7
6
5
MULTICAST_ADDRESS[47:32]
Default Value
All 0s
All 0s
0
9
8
7
6
5
Default Value
1: When TIEEMAC#CONFIGVEC[64]
is set to 0
0: When TIEEMAC#CONFIGVEC[64]
is set to 1
(Figure
3-40).
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
R
4
3
2
1
0
R/W
R/W
4
3
2
1
0
R/W
R/W
R/W
R/W
4
3
2
1
0
R/W
R/W

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