Xilinx Virtex-4 User Manual page 30

Chapter 2: Ethernet MAC Architecture
Table 2-11: MAC Configuration Pins
Signal
TIEEMAC#CONFIGVEC[64]
TIEEMAC#CONFIGVEC[63]
TIEEMAC#CONFIGVEC[62:61] — These pins configure the Ethernet MAC flow control module.
TIEEMAC#CONFIGVEC[62]
TIEEMAC#CONFIGVEC[61]
TIEEMAC#CONFIGVEC[60:54] — Configures the transmit engine of the Ethernet MAC.
TIEEMAC#CONFIGVEC[60]
TIEEMAC#CONFIGVEC[59]
TIEEMAC#CONFIGVEC[58]
TIEEMAC#CONFIGVEC[57]
TIEEMAC#CONFIGVEC[56]
TIEEMAC#CONFIGVEC[55]
TIEEMAC#CONFIGVEC[54]
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Direction
Address Filter Enable: Asserting this pin enables the use of the
Input
address filter module in the Ethernet MAC.
Length/Type Check Disable: When this pin is asserted, it
Input
disables the comparison of the L/T field with the size of the data.
Receive Flow Control Enable. When this bit is
mode is enabled,
Input
transmitter operation. When this bit is 0, the received flow
frames are passed up to the client.
Transmit Flow Control Enable. When this bit is
mode is enabled,
Input signal causes the Ethernet MAC to send a flow control frame out
from the transmitter. When 0, asserting the
CLIENTEMAC#PAUSE_REQ signal has no effect.
Transmitter Reset. When this bit is
Input transmitter is held in reset. This signal is an input to the reset
circuit for the transmitter block.
Transmitter Jumbo Frame Enable. When this bit is 1, the Ethernet
MAC transmitter allows frames larger than the maximum legal
Input frame length specified in IEEE Std 802.3-2002 to be sent. When
this bit is 0, the Ethernet MAC transmitter only allows frames up
to the legal maximum to be sent.
Transmitter In-Band FCS Enable. When this bit is
MAC transmitter expects the FCS field to be passed in by the
Input client. When this bit is 0, the Ethernet MAC transmitter appends
padding as required, computes the FCS, and appends it to the
frame.
Transmitter Enable. When this bit is
Input
operational. When this bit is 0, the transmitter is disabled.
Transmitter VLAN Enable. When this bit is
Input
allows the transmission of VLAN tagged frames.
Transmitter Half Duplex. When this bit is
Input operates in half-duplex mode. When this bit is 0, the transmitter
operates in full-duplex mode.
Transmitter IFG Adjust enable. When this bit is
reads the value of the CLIENTEMAC#TXIFGDELAY[7:0] port
Input
and sets the IFG accordingly. When this bit is 0, the transmitter
always inserts at least the legal minimum IFG.
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Description
the received flow control frames inhibit
asserting the CLIENTEMAC#PAUSE_REQ
the Ethernet MAC
1,
the transmitter is
1,
1,
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
R
1 and full-duplex
1 and full duplex
the Ethernet
1,
the transmitter
1,
the transmitter
the transmitter
1,