Xilinx Virtex-4 User Manual page 57

R
EMACCLIENT#RXCLIENTCLKOUT as an input, the divide-by-two clock signal is
generated. See
Figure 3-22
number of bytes in the frame.
CLIENTEMAC#RXCLIENTCLKIN
PHYEMAC#RXCLK
(CLIENTEMAC#RXCLIENTCLKIN/2)
EMAC#CLIENTRXD[15:0]
EMAC#CLIENTRXDVLD
EMAC#CLIENTRXDVLDMSW
EMAC#CLIENTRXGOODFRAME
EMAC#CLIENTRXBADFRAME
Figure 3-23
number of bytes in the frame.
CLIENTEMAC#RXCLIENTCLKIN
PHYEMAC#RXCLK
(CLIENTEMAC#RXCLIENTCLKIN/2)
EMAC#CLIENTRXD[15:0]
EMAC#CLIENTRXDVLD
EMAC#CLIENTRXDVLD MSW
EMAC#CLIENTRXGOODFRAME
EMAC#CLIENTRXBADFRAME
As shown in
an odd number of bytes in the frame. The data valid signals are shown in the even byte
case
deasserted one clock cycle earlier compared to the EMAC#CLIENTRXDVLD signal, after
the reception of the frame. EMAC#CLIENTRXD[7:0] contains the data in this odd byte
case.
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Figure 4-28, page 139
shows the timing of a normal inbound frame transfer for the case with an even
DA
Figure 3-22: 16-Bit Receive (Even Byte Case)
shows the timing of a normal inbound frame transfer for the case with an odd
DA
Figure 3-23: 16-Bit Receive (Odd Byte Case)
Figure 3-22 and Figure
(Figure 3-22). In the odd byte case
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for more information.
SA DATA
SA DATA
3-23, EMAC#CLIENTRXDVLDMSW is used to denote
(Figure 3-23), EMAC#CLIENTRXDVLDMSW is
Client Interface
ug074_3_24_082007
ug074_3_25_080805
57