Clock Signals - Xilinx Virtex-4 User Manual

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Clock Signals

Table 2-4
Table 2-4: Clock Signals
Signal
PHYEMAC#GTXCLK
EMAC#CLIENTRXCLIENTCLKOUT
EMAC#CLIENTTXCLIENTCLKOUT
CLIENTEMAC#RXCLIENTCLKIN
CLIENTEMAC#TXCLIENTCLKIN
EMAC#CLIENTTXGMIIMIICLKOUT
CLIENTEMAC#TXGMIIMIICLKIN
Notes:
1. The Ethernet MAC uses this clock to generate an internal clock that eliminates clock skew between the Ethernet MAC and the client
logic in the FPGA.
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
shows the clock signals necessary to drive the Ethernet MAC.
Direction
Clock supplied by the user to derive the other transmit clocks.
Input Clock tolerance must be within the IEEE Std 802.3-2002
specification.
Clock for receive client generated by the clock generator of the
Output
Ethernet MAC.
Clock for transmit client generated by the clock generator of the
Output
Ethernet MAC.
Clock from receive client for the running of the receiver engine of
Input
the Ethernet MAC.
Clock from transmit client for the running of the transmitter
Input
engine of the Ethernet MAC.
Clock for MII, GMII, and RGMII modules. Generated by the clock
Output
generator of the Ethernet MAC.
Clock from MII, GMII, and RGMII modules for the running of the
Input
MII/GMII/RGMII transmitter layer of the Ethernet MAC.
www.xilinx.com
Ethernet MAC Signal Descriptions
Description
(1)
(1)
(1)
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