Xilinx Virtex-4 User Manual page 4

Date Version
02/07/06 1.4 In
• Added EMAC#CLIENTRXCLIENTCLKOUT to
In
• Corrected
• Inserted new text to
• Edited waveforms in
• Added sections to
• Added
• Added IDELAY component to
• Revised the GT11 block in
In
• Replaced
• Revised example code in
In
• Added new text to
• Added
• Replaced
• Replaced
02/09/06 1.4.1 Cleaned up formatting issues. No content changes.
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
Chapter 2, "Ethernet MAC
Chapter 5, "Miscellaneous
"Client RX Data/Control Interface," page
"Length/Type Field Error Checks," page
page 115, and "10/100/1000 SGMII Clock Management," page
Figure 3-39, page
Table 3-36, page
"Introduction to MDIO," page
"Tri-Mode Operation with Byte PHY Enabled (Full-Duplex Only)," page
"1000BASE-X PCS/PMA (8-bit Data Client) Clock Management," page
SGMII Clock Management," page
Client," page 130.
Chapter 6, "Use Models":
"Interfacing to an FPGA Fabric-Based Statistics Block," page 154
content.
"Writing to the PHY Registers Using MDIO," page
Chapter 7, "Ethernet MAC
"VHDL and Verilog CORE Generator Wrappers," page
"Advanced Clocking," page 155
"File Generation"
Figure 5-1, page
www.xilinx.com
Revision
Architecture":
Table 2-2, page
Functions":
66.
88.
90, "MDIO Implementation in the EMAC," page
Figure 3-61, Figure 3-62,
Figure 3-72 and Figure 3-73. Modified text in
121, "8-Bit Data Client," page
Wrappers":
and "Client Side Data Width," page 157
with new content.
153.
19.
55.
52, "Tri-Mode RGMII v2.0,"
121.
109, and
126.
Figure 3-63, and Figure
"10/100/1000
129, and "16-Bit Data
with new
153.
159.
UG074 (v2.2) February 22, 2010
92,
3-64.
options.