Xilinx Virtex-4 User Manual page 139

R
16-Bit Data Client
Figure 4-28
and a 16-bit data client. This mode supports 1.25 Gb/s and 2.5 Gb/s line rates. For a
2.5 Gb/s line rate, clock and data are recovered from the incoming data stream.
250 MHz
'0'
BUFG
'0'
PHYEMAC#GTXCLK
EMAC#CLIENTTXCMIIMIICLKOUT
X
CLIENTEMAC#DCMLOCKED
CLIENTEMAC#TXGMIIMIICLKIN
RESET
Figure 4-28: 1000BASE-X PCS/PMA (16-Bit Data Client) Clock Management
The inputs of the GT11CLK_MGT primitive connect to an external, high-quality reference
clock with a frequency of 250 MHz for 1.25 Gb/s and 2.5 Gb/s line rates. The output
SYNCLK1OUT connects to the PLL reference clock input REFCLK1. TXOUTCLK1,
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Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
shows the clock management used with the 1000BASE-X PCS/PMA interface
MGTCLKP SYNCLK1OUT
MGTCLKN
GT11CLK_MGT
REFCLK1
RXUSRCLK2
RXUSRCLK
TXOUTCLK1 TXLOCK
TXUSRCLK2 RXLOCK
TXUSRCLK
GT11
CLIENTEMAC#TXCLIENTCLKIN
EMAC#CLIENTTXCLIENTCLKOUT
PHYEMAC#MIITXCLK
CLIENTEMAC#RXCLIENTCLKIN
EMAC#CLIENTRXCLIENTCLKOUT
PHYEMAC#RXCLK
Ethernet MAC
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1000BASE-X PCS/PMA
CLK0
CLKFB
CLKIN
Locked
BUFG
CLKDV
DCM
X
BUFG
BUFG
UG074_3_64_012408
139