Xilinx Virtex-4 User Manual page 38

Chapter 3: Client, Host, and MDIO Interfaces
CLIENTEMAC#TXCLIENTCLKIN
PHYEMAC#MIITXCLK
CLIENTEMAC#TXD[15:0]
CLIENTEMAC#TXDVLDMSW
CLIENTEMAC#TXDVLD
EMAC#CLIENTTXACK
EMAC#CLIENTTXRETRANSMIT
EMAC#CLIENTTXCOLLISION
CLIENTEMAC#TXUNDERRUN
CLIENTEMAC#TXFIRSTBYTE
TIEEMAC#CONFIGVEC[66]
CLIENTEMAC#TXIFGDELAY[7:0]
FPGA Fabric
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38
CLIENT
Transmit
Client
Interface
Ethernet MAC Block
Figure 3-1: Transmit Client Block Diagram
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TX_DATA_VALID
Transmit
(Internal Signal)
Engine
TX_DATA[7:0]
(Internal Signal)
TX_ACK_EARLY
(Internal Signal)
TX_ACK
(Internal signal)
TX_RETRANSMIT
(Internal Signal)
TX_COLLISION
(Internal Signal)
TX_UNDERRUN
(Internal Signal)
TXFIRSTBYTEREG
(Internal Signal)
TX_IFG_DELAY[7:0]
(Internal Signal)
Embedded Tri-Mode Ethernet MAC User Guide
PHY
PHYEMAC#GTXCLK
EMAC#PHYTXCLK
EMAC#PHYTXD[7:0]
EMAC#PHYTXEN
EMAC#PHYTXER
ug074_3_03_070105
UG074 (v2.2) February 22, 2010
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