Interfacing To An Fpga Fabric-Based Statistics Block; When The Ethernet Mac Is Implemented With The Host Bus - Xilinx Virtex-4 User Manual

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Interfacing to an FPGA Fabric-Based Statistics Block

When the Ethernet MAC Is Implemented with the Host Bus

When the Ethernet MAC is used with the host bus, interfacing to a fabric-based statistics
block is straight forward. Statistics information is passed from the Ethernet MAC via the
statistics vectors EMAC#CLIENTTXSTATS and EMAC#CLIENTRXSTATS. The statistics
values can then be read via a host interface, shared between the statistics counters and the
Ethernet MAC block.
To share the host bus without contention, statistics counters need to use a different address
space than the Ethernet MAC configuration registers. Conflicts with MDIO register access
are avoided by only accessing statistics counters when the signal HOSTMIIMSEL is at
logic 0. Implementation of the addressing scheme shown in
bus can be shared without contention. This scheme provides space to address 512 statistics
counters per Ethernet MAC, using addresses 0x000 to 0x1FF.
Table 6-1: Addressing Scheme
Figure 6-1
Statistics block, where the Ethernet statistics counters are accessed via the host bus. The
LogiCORE Ethernet Statistics block is used with the addressing scheme shown in
Table
the Ethernet Statistics LogiCORE block.
Statistics blocks to both Ethernet MACs within the Ethernet MAC block. If statistics are
required for only one Ethernet MAC, then the multiplexing between the statistics cores is
simply replaced with a straight-through connection.
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Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
// Write the PHY address and PHY register to be accessed to the
// dataRegLSW register
mtdcr(0x0 + 13, 0x00000020);
// Write the decode address for MDIO address output to the cntlReg
// register
mtdcr(0x0 + 14, 0x87B4);
// Poll the RDYstatus register
while ( !(mfdcr(0x0 + 15) & 0x00000400) );
Transaction
Configuration
MIIM Access
Statistics Access
shows how to integrate the Ethernet MAC with the LogiCORE Ethernet
6-1. DS323, LogiCORE Ethernet Statistics Data Sheet, provides a a full description of
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Interfacing to an FPGA Fabric-Based Statistics Block
Host_miim_sel
0
1
0
Figure 6-1 illustrates how to connect Ethernet
Table 6-1 ensures that the host
Host_addr[9]
1
X
0
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