Xilinx Virtex-4 User Manual page 129

R
MGT Logic Using the MGT RX Elastic Buffer
Figure 4-23
Connections to the RocketIO transceiver are illustrated.
Ethernet MAC
(PCS/PMA Sublayer)
EMAC#PHYSYNCACQSTATUS
EMAC#PHYTXD[7:0]
EMAC#PHYLOOPBACKMSB
EMAC#PHYPOWERDOWN
EMAC#PHYTXCHARDISPMODE
EMAC#PHYTXCHARDISPVAL
EMAC#PHYTXCHARISK
PHYEMAC#TXBUFERR
PHYEMAC#COL
PHYEMAC#RXD[7:0]
PHYEMAC#RXRUNDISP
PHYEMAC#RXCHARISK
PHYEMAC#RXCLKCORCNT[2:0]
PHYEMAC#RXCHARISCOMMA
PHYEMAC#RXBUFSTATUS[1]
PHYEMAC#DISPERR
PHYEMAC#RXNOTINTABLE
PHYEMAC#RXCHECKINGCRC
PHYEMAC#RXLOSSOFSYNC[1:0]
PHYEMAC#RXCOMMADET
PHYEMAC#RXBUFSTATUS[0]
PHYEMAC#RXBUFFERR
These connections and the shim are created by the CORE Generator tool when the physical
interface is selected to be either SGMII or 1000BASE-X PCS/PMA. By using the CORE
Generator tool, the time required to instantiate the Ethernet MAC into a usable design is
greatly reduced.
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
10/100/1000 Serial Gigabit Media Independent Interface (SGMII)
shows the Ethernet MAC configured with SGMII as the physical interface.
Status
Only
Shim
Reset
State
Machine
GND
Figure 4-22: Ethernet MAC Configured in SGMII Mode
www.xilinx.com
GT11 Transceiver
TXDATA#[7:0]
LOOPBACK#[0]
TXPOWERDOWN#
TXCHARDISPMODE#[0]
TXCHARDISPVAL#[0]
TXCHARISK#[0]
TXBUFSTATUS#[1]
TXRUNDISP#[0]
RXSTATUS
RXDATA#[7:0]
RXRUNDISP#[0]
RXCHARISK#[0]
RXCHARISCOMMA#[0]
RXBUFERR
RXDISPERR#[0]
RXNOTINABLE#[0]
RXRESET
TXRESET
MGTCLK_P
MGTCLK_N
TXN_#
TXP_#
RXN_#
RXP_#
UG194_6_29_103106
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