Xilinx Virtex-4 User Manual page 60

Chapter 3: Client, Host, and MDIO Interfaces
Figure 3-25
(16-bit mode). The address filter is disabled in this timing diagram.
CLIENTEMAC#RXCLIENTCLKIN
PHYEMAC#RXCLK
EMAC#CLIENTRXDVLD
EMAC#CLIENTRXDVLDMSW
EMAC#CLIENTRXD[15:0]
EMAC#CLIENTRXGOODFRAME
EMAC#CLIENTRXFRAMEDROP
Figure 3-25: Frame Matching Timing Diagram (16-Bit Mode)
Figure 3-26
AF (8-bit mode) and the frame drop signal is generated. The address filter is disabled in
this timing diagram.
CLIENTEMAC#RXCLIENTCLKIN
EMAC#CLIENTRXDVLD
EMAC#CLIENTRXD[7:0]
EMAC#CLIENTRXGOODFRAME
EMAC#CLIENTRXFRAMEDROP
Figure 3-26: Frame Matching Failed Timing Diagram (8-Bit Mode)
www.BDTIC.com/XILINX
60
shows the timing diagram when a frame matches a valid location in the AF
Previous Frame
Dropped
shows the timing diagram when a frame fails to match a valid location in the
Previous Frame
Passed
www.xilinx.com
n–5 n–4 n–3 n–2 n–1 n n+1 n+2 n+3 n+4 n+5 n+6
DA1, DA0 DA3, DA2 DA5, DA4
n–2 n–1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7
DA
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
DA
Current Frame
Passed
ug074_3_27_080805
SA
Current Frame
Dropped
ug074_3_28_080805
R