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Use Models
This chapter contains the following sections:
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Simulation Models
SecureIP Model
SecureIP models are encrypted versions of the actual HDL code. These models allow the
user to simulate the functionality of the design without the overhead of simulating RTL. A
Verilog LRM-IEEE 1364-2005 encryption-compliant simulator is required to use SecureIP.
The SecureIP model of the Ethernet MAC is installed with Xilinx® tools and can be
precompiled into UniSim and SimPrim libraries. These libraries are used for functional
and timing simulations, respectively. VHDL and Verilog wrappers are generated by the
CORE Generator™ tool in the ISE software, as well as the scripts to simulate the Secure IP
model.
For further help using the Ethernet MAC SecureIP model, see the documentation supplied
with ISE software, especially the Synthesis and Simulation Design Guide at:
http://www.xilinx.com/support/software_manuals.htm.
Model Considerations
The DCR bus, except for DCREMACENABLE, is internally connected to the PPC405
processor in the Virtex-4 FPGA processor block. However, for the SecureIP model of the
Ethernet MAC, the user has to connect the DCR portion with the SecureIP model of the
PowerPC 405 processor including DCREMACENABLE.
When simulating with the PCS/PMA layer (i.e., the Ethernet MAC is configured in either
SGMII or 1000BASE-X PCS/PMA mode) and auto-negotiation is initialized to OFF
(TIEEMAC#CONFIGVEC[77] = 0), EMAC#PHYSYNCACQSTATUS waits to be asserted
High before the start of transmission. This allows the PCS layer to obtain synchronization.
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
"Simulation Models"
"Pinout Guidelines"
"Interfacing to the Processor DCR"
"Interfacing to an FPGA Fabric-Based Statistics Block"
www.xilinx.com
Chapter 6
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