Ps-Side: Gtr Transceivers - Xilinx ZCU111 User Manual

SFP28
One PL-side GTY transceiver in bank 128 is provided for the quad SFP28 interface. Available
GTY reference clocks include a jitter attenuated recovered clock from a Si5382. SFP+
modules typically provide an I2C based control interface. This I2C interface is accessible for
each individual SFP28 module through the I2C multiplexer topology on the ZCU111 board.
The RFSoC U1 connections for each quad are referenced in
Constraints.
For additional information on GTY transceivers, see the UltraScale Architecture GTY
Transceivers User Guide (UG578)

PS-Side: GTR Transceivers

[Figure 2-1, callout 1]
The PS-side GTR transceiver bank 505 supports two DisplayPort transmit channels, USB (3.0)
and SATA, as shown in
ZCU111 Board User Guide
UG1271 (v1.1) August 6, 2018
[Ref 6].
Figure 3-30.
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Chapter 3: Board Component Descriptions
Appendix B, Xilinx Design
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