Intel Nios V Quick Start Manual

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Nios

V Processor Quick Start Guide

Updated for Intel

Quartus

Prime Design Suite: 21.3

IP Version: 21.1.0

UG-20345 | 2021.10.04

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Summary of Contents for Intel Nios V

Page 1 ® Nios V Processor Quick Start Guide ® ® Updated for Intel Quartus Prime Design Suite: 21.3 IP Version: 21.1.0 Subscribe UG-20345 | 2021.10.04 Send Feedback Latest document on the web: HTML...
Page 2: Table Of Contents
3. Nios V/m Processor Example Design................6 3.1. Generating the Example Design Through Graphical User Interface........ 7 3.1.1. Generating the Nios V/m Processor Example Design in Platform Designer..7 3.1.2. Generating the Nios V/m Processor Example Design System in Platform Designer....................8...
Page 3: About This Document
Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
Page 4: System Requirements
Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
Page 5 Table 2. PATH Variable Setup Examples Open-source tool PATH variable setup GNU RISC-V Embedded GCC Windows command prompt: v8.3.0-2.3 set PATH=<Intel Quartus Prime installation directory>/niosv/xpack-riscv-none-embed- gcc-8.3.0-2.3/bin;%PATH% Linux terminal: export PATH=<Intel Quartus Prime installation directory>/niosv/xpack-riscv-none- embed-gcc-8.3.0-2.3/bin:$PATH CMake v3.21.1 Windows command prompt: set PATH=<Intel Quartus Prime installation directory>/niosv/cmake-3.21.1-windows-...
Page 6: Nios V/M Processor Example Design
Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
Page 7: Generating The Example Design Through Graphical User Interface
3. Nios V/m Processor Example Design UG-20345 | 2021.10.04 3.1. Generating the Example Design Through Graphical User Interface 3.1.1. Generating the Nios V/m Processor Example Design in Platform Designer 1. In the Intel Quartus Prime software, go to Tools Platform Designer.
Page 8: Generating The Nios V/M Processor Example Design System In Platform Designer
) file. top.sdc .sdc Top-level Verilog design. top.v 3.1.2. Generating the Nios V/m Processor Example Design System in Platform Designer 1. Open the project, go to Tool Platform Designer. 2. Create a new Platform Designer system and name it as sys.qsys...
Page 9 Nios V example design that is enabled with Memory initialization file (.hex). 8. Click Generate HDL to generate the system HDL. Note: If you are using other Intel FPGA IP device, update the FAMILY, DEVICE, and clock pin assignments in the file.
Page 10: Generating The Nios V/M Processor Example Design Using The Command-Line Interface
--flow compile top Note: For Linux environment, you must exit the Nios V Command Shell before compiling a project. Do not perform any design compilation within Nios V Command Shell in Linux. For more information, refer to KDB link: Why does the Quartus project compilation failed in Intel Quartus Prime Pro (Linux version) within Nios V Command Shell?.
Page 11: Software Design Flow
Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
Page 12 4. Software Design Flow UG-20345 | 2021.10.04 Figure 4. Create New BSP window 10. Click Generate BSP to generate the BSP file. ® Nios V Processor Quick Start Guide Send Feedback...
Page 13: Generating The Board Support Package Using The Command-Line Interface
UG-20345 | 2021.10.04 Figure 5. BSP Editor Note: In the BSP Editor, the default selection for sys_clk_timer and timestamp_timer are configured to cpu to use the Nios V/m processor's internal timer. Related Information Intel Quartus Prime Pro Edition User Guide: Platform Designer More information about Creating a Board Support Package with BSP Editor.
Page 14: Building The Application Project
Related Information Nios V processor tool setup for Eclipse Embedded CDT and OpenOCD For more guidance about Eclipse Embedded CDT, refer to RocketBoards.org 4.3.2. Building the Application Project using the Command-Line Interface You can also build the “Hello World” application using the CLI command: 1.
Page 15: Programming, Memory Initialization, Simulation, And Debug
Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
Page 16: Memory Initialization
5. Programming, Memory Initialization, Simulation, and Debug UG-20345 | 2021.10.04 4. Use the JTAG UART terminal to print the stdout and stderr of the Nios V/m processor system. juart-terminal 5. The Hello World application displays as shown in the following figures.
Page 17 At User created initialization file, browse to the created file. ram.hex Figure 8. IP Parameter Editor for On-Chip Memory (RAM or ROM) Intel FPGA IP 3. Go to Processing Start Compilation or run quartus_sh --flow compile to perform a full hardware compilation and generate the file with .sof...
Page 18: Simulation
15. After programming, reset the FPGA device, and the application should start running. Use the JTAG UART terminal to print the stdout and stderr of the Nios V/m processor system. 5.3. Simulation 1. To generate the simulation files, follow these steps: a.
Page 19: Debug
Following figure is the example output of the certain selected signals: Figure 10. Signal Output in Questa (Intel FPGA Edition) 5.4. Debug Refer to the related information for more information about how to use OpenOCD to debug Nios V/m processor application.
Page 20: Nios V/M Processor Reference
Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.
Page 21: Hardware Abstraction Layer (Hal) Driver
BSP. Intel recommends you to use the BSP Editor in Platform Designer to manage and modify the BSP .
Page 22: Document Revision History For Nios V Processor Quick Start Guide
Intel's standard warranty, but reserves the right to make changes to any 9001:2015 products and services at any time without notice. Intel assumes no responsibility or liability arising out of the Registered application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.