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Figure 2.6
DMA Target Mode Transfers
Enable Parity Checking, Enable Parity
Interrupts May Be Set at this Time
Target Receive
(Data Out Phase)
Reset Assert I_O/,
MSG/, and C_D/ Bits
(0xFC03 Bits [2:0]
Write to Start DMA
Target Receive
Register (0xFC06)
2-12
Write IMR
(0xFE0D) to Enable
only DMA Interrupts
Write Transfer
Length to DTL
Register (0xFC11)
Write Source/
Destination Addresses
to 0xFC12, 0xFC13
Set TIP Bit In
0xFC10 Bit 0
Set DM, and
TGTM Bits
(0xFC02 Bits 6, 1)
Target Send
(Data In Phase)
Set Assert I_O Bit
Reset C_D/
and MSG/
(0xFC03 Bits [2:0]
Set ADB Bit
(Reg. 0xFC01, Bit 0)
Write to DMA Send
Register (0xFC05)
A
Functional Description
A
Set Bit 1 in Register
0x87 of the
Microprocessor
Core to Put It into
Power Down Mode
Wait for an Interrupt
DMA
Interrupt
?
Yes
ISR - Clear Interrupt
(0xFC0E)
TC Bit Set?
(0xFC10 Bit 3)
Yes
Reset DMA
Mode Bit
(0xFC02 Bit 1)
Reset Assert
Data Bus Bit
(0xFC01 Bit 0)
Enable Other
Necessary Interrupts
That Were Disabled
for DMA Transfer
No
Error Recovery
Target Send Only
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