Table of Contents
Advertisement
6-8
Register: 0xFD01/0xFD03
Status Register Reads (ES0 = 1)
Read Only
7
6
PIN
RPSS
0
0
PIN
Pending Interrupt Not
This active low bit is cleared when the Data Register has
completed an operation and requires microcontroller
intervention to continue operation.
RPSS
Repeated Start
This bit indicates that a repeated start condition occurred
on the bus, but only when this interface was involved in
the original transfer.
STS
Slave Mode Stop
This bit is set if the STOP condition is detected when the
SYM53C040 is in slave receive mode.
BER
Bus Error Detection
This bit is set if a bus error is detected by the
SYM53C040, (i.e., Misplaced Start or Stop). Setting this
bit clears the BB_N bit and resets the PIN bit.
LRB/AD0
Last Received Bit/Address 0 Bit
This bit specifies one of the following, depending on the
state of the protocol when this bit is set (for more
information, refer to
•
If the slave selection address was the preprogrammed
Own Address register value (logic 0) or the General
Call address (logic 1) during Slave Selection
operation, this bit indicates a read (1) or write (0)
request.
•
The last bit received during data transfer. Useful for
testing ACK reception from a slave device.
AAS
Addressed as Slave
When active (1), this bit signifies that an address was
received across the two-wire data register interface that
Two-Wire Serial Registers
5
4
3
STS
BER
LRB/AD0
Defaults:
0
0
0
Figure
2
1
AAS
LAB
0
0
2.11,
page
2-19).
0
BB_N
0
7
6
5
4
3
2
Advertisement
Table of Contents
