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Register: 0xFE00
Watchdog Timer Control (WDTC)
Read/Write
7
6
WDRBT
0
0
The SYM53C040 includes a built-in watchdog timer, which causes a soft
reset when it expires. If the watchdog timer expires and forces a chip
reset, the reset pad will also assert a low output for resetting other
external functions if the Enable Reset Output bit is set (0xFF05, bit 7). If
the watchdog timer is used, the SYM53C040 firmware needs to
periodically clear the watchdog timer. The watchdog timer reinitializes the
SYM53C040 if the firmware does not clear the timer before time-out. The
watchdog timer is cleared with any write to the
(WDTC)
register. This register is not affected by a soft reset.
In hardware, the timer consists of three divider chains. The primary
divider divides the system clock by a factor of 4000, yielding a 10 kHz
clock to the secondary chain when the internal system clock is 40 MHz.
The secondary chain divides the primary chain output by a factor of 100,
yielding a 100 Hz clock. The final chain divides the secondary chain by
the programmable value in the
represented by bits 3 through 0.
WDRBT
Watchdog Reboot
This read/write register bit, when set, indicates that the
SYM53C040 has performed a soft reset, or reboot, due
to expiration of the watchdog timer. This bit can be
cleared or set by firmware.
R
Reserved
WTHR[3:0]
Watchdog Timer Threshold
The 4-bit value stored in bits 3 through 0 of the WDTC
register define the watchdog timer threshold. A value of
0 in all bits disables the watchdog timer. The watchdog
timer can be programmed for 15 different time-out values
between 10 ms and 150 ms, in steps of 10 ms.
shows the possible time-out values.
4
3
R
WTHR3
Defaults:
0
0
0
Watchdog Timer Control
2
1
WTHR2
WTHR1
WTHR0
0
0
Watchdog Timer Control
(WDTC),
Table 7.3
0
0
7
[6:4]
[3:0]
7-3
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