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Register: 0xFF13
Multipurpose I/O Bank 1 Latch Mask (MPLM1)
Read/Write
7
6
MPLM1_7 MPLM1_6 MPLM1_5 MPLM1_4 MPLM1_3 MPLM1_2 MPLM1_1 MPLM1_0
1
1
MPLM1_[7:0] Multipurpose I/O Bank 1 Latch Mask
These read/write register bits define the write mask for
the
Multipurpose I/O Bank 1 Latch (MPL1)
(0xFF14). A value of 1 in any of these bits allows the
corresponding bit in the MPL1 to be modified.
Register: 0xFF14
Multipurpose I/O Bank 1 Latch (MPL1)
Read/Write
7
6
MPL1_7
MPL1_6
MPL1_5
x
x
MPL1_[7:0]
Multipurpose I/O Bank 1 Latch
These read/write register bits store the power-on value of
the I/O pins MPIO1_0, MPIO1_1, MPIO1_2, MPIO1_3,
MPIO1_4, MPIO1_5, MPIO1_6, and MPIO1_7. The
values on these pins are latched into this register on the
deasserting edge of the RESET/ input signal or the
internal power-on reset.
5
4
3
Defaults:
1
1
1
5
4
3
MPL1_4
MPL1_3
Defaults:
x
x
x
2
1
1
1
register
2
1
MPL1_2
MPL1_1
MPL1_0
x
x
0
1
[7:0]
0
x
[7:0]
8-13
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