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7-10
Register: 0xFE07
Timer 1 Secondary Chain (T1SC)
Read Only
7
6
R
T1SC6
x
0
R
Reserved
T1SC[6:0]
Timer 1 Secondary Chain
These register bits provide the ability to read the
secondary divide by 100 chain of timer 1. This chain is
enabled with the T1PS bit (0xFE05, bit 4). When enabled,
a value of 100 (decimal) in this register triggers
advancement of the final timer 1 divider chain.
Register: 0xFE08
Timer 1 Final Chain (T1FC)
Read Only
7
6
T1FC7
T1FC6
0
0
T1FC[7:0]
Timer 1 Final Chain
These register bits provide the ability to read the final
timer 1 divider chain. The timer expires when the value
of this divider chain is equal to the value of the
Threshold (T1TH)
the T1EXP bit (0xFE05, bit 7) will be set and an interrupt
will be generated to the microcontroller, through the
rupt Status (ISR)
is set.
Miscellaneous Registers
5
4
T1SC5
T1SC4
T1SC3
Defaults:
0
0
5
4
T1FC5
T1FC4
T1FC3
Defaults:
0
0
register (0xFE06). When this happens,
register, if the T1IEN bit (0xFE05, bit 0)
3
2
1
T1SC2
T1SC1
0
0
0
3
2
1
T1FC2
T1FC1
0
0
0
0
T1SC0
0
7
[6:0]
0
T1FC0
0
[7:0]
Timer 1
Inter-
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