Jtag Signals - LSI Symbios SYM53C040 Technical Manual

3.1.3 JTAG Signals

Table 3.7

JTAG Signals

Pin Pin
Name Number
TCK 91
TMS 90
TDI 92
TDO 89
TRST/ 151
3-16
Table 3.7 describes the signals for the JTAG Signals group.
BGA Ball
Number
J13 Test Clock. The Test Clock pin
provides clocking for the JTAG test
logic and boundary scan.
J12 Test Mode Select. The Test Mode
Select pin receives a signal to
control the JTAG test operations and
boundary scans.
H10 Test Data In. The Test Data In pin
receives serial input data and
commands for JTAG test operations
and boundary scans.
J11 Test Data Out. The Test Data Out pin
provides serial output data for JTAG
test operations and boundary scans.
C5 Test Reset. The Test Reset pin
receives a signal to reset the JTAG
TAP controller. It also simulates a
power-on reset for core logic (NOTE:
not JTAG compliant).
Signal Descriptions
Description
Internal
Pad Type Resistor
100 µA
5 V
tolerant pull-up
TTL input
100 µA
5 V
tolerant pull-up
TTL input
100 µA
5 V
tolerant pull-up
TTL input
4 mA None
Output
100 µA
5 V
tolerant pull-up
TTL input