Table of Contents
Advertisement
Table 3.9
Pin Assignments for SFF-8067 Mode (Cont.)
Pin/Ball
Signal Name
No.
D1, SEL_1
136/A8
D2, SEL_2
135/B8
D3, SEL_3
134/C8
ENCL_ACK/,
132/D8
SEL_4
DSK_RD/,
131/A9
SEL_5
3-20
Description
When PARALLEL_ESI/ is asserted,
this signal contains bit 1 of a data
nibble for read and write operations.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_1
signal, included for compatibility with
SFF-8045.
When PARALLEL_ESI/ is asserted,
this signal contains bit 2 of a data
nibble for read and write operations.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_2
signal, included for compatibility with
SFF-8045.
When PARALLEL_ESI/ is asserted,
this signal contains bit 3 of a data
nibble for read and write operations.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_3
signal, included for compatibility with
SFF-8045.
When PARALLEL_ESI/ is asserted,
this is an active low acknowledge
signal sourced by the SYM53C040
back to the Fibre Channel device.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_4
signal, included for compatibility with
SFF-8045.
When PARALLEL_ESI/ is asserted,
this is an active low control signal
sourced by the drive to the
SYM53C040 to indicate the device
is ready to read data. When
PARALLEL_ESI/ is deasserted, this
signal is the SEL_5 signal, included
for compatibility with SFF-8045.
Signal Descriptions
8067 Port
Configuration
Port 1
4 mA open drain
bidirectional
Port 1
4 mA open drain
bidirectional
Port 1
4 mA open drain
bidirectional
Port 1
4 mA open drain
bidirectional
Port 1
4 mA open drain
bidirectional
Pad
Advertisement
Table of Contents
